Run cards of the FlexFET process

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Standard steps of the process

Step 1. Starting wafers

Step 2. Scribe wafers

Split point # 1. Thin SOI vs. Thick SOI

Step 3. Thin SOI sacrificial oxidation

Step 4. Wet strip sacrificial oxide

Step 5. Zero layer photo

Step 6. Zero layer etch

Step 7. Resist strip and clean

Split point # 2.  Implanted S/D vs. Silicided S/D

Step 8. Screen oxidation

Step 9. NMOS photo

Step 10. N+ S/D implant

Step 11. Resist strip and clean

Step 12. PMOS photo

Step 13. P+ S/D implant

Step 14. Resist strip and clean

Step 15. Sputter titanium

Step 16. Implanted S/D activation

Step 17a. Nitride pad deposition onto imp. S/D wafers

Step 17b. Nitride pad deposition onto Silicided wafers

Step 18a. Active area photo on imp. S/D wafers

Step 18b. Active are photo on Silicided wafers

Step 19a. Nitride pad etch on imp. S/D wafers

Step 19b. Nitride pad etch on Silicided wafers

Step 20a. Silicon etch on imp. S/D wafers

Step 20b. Ti etch on Silicided S/D wafers

Step 21. RTA silicide reaction on Silicided S/D wafers

Step 22. Resist strip and clean

Step 23. N+ spacer deposition

Step 24. PSG spacer etch

Step 25. PMOS photo

Step 26. PMOS bottom gate and Vt adjustment implants

Step 27. Wet etch PSG from PMOS region

Step 28. Resist strip and clean

Step 29. RTA PSG & PMOS drive

Step 30. Strip PSG

Step 31. BSG spacer deposition

Step 32. BSG spacer etch

Step 33. NMOS photo

Step 34. NMOS bottom gate and Vt adjustment implant

Step 35. Wet etch BSG from NMOS region

Step 36. Resist strip and clean

Step 37. RTA BSG and NMOS drive out

Step 38. Strip BSG

Step 39. Bottom gate photo

Step 40. Silicon etch to BOX

Step 41. Resist strip and clean

Step 42. Sacrificial oxidation

Step 43. Nitride spacer deposition

Step 44. Nitride spacer etch

Step 45. Sacrificial oxide strip and clean

Step 46. Gate oxidation

Step 47a. Poly-Si topgate deposition

Step 47b. TiN+Poly-Si topgate deposition

Step 48. Topgate photo 

Step 49. Top gate etch

Step 50. Resist strip and clean

Step 51. TEOS oxide STI deposition

Step 52. STI oxide planarization

Step 53. Gate contact (M0) photo

Step 54. STI oxide etch

Step 55. Resist strip and clean

Step 56. M0 deposition (PVD TiN and LPCVD Poly-Si)

Step 57. M0 CMP (Poly and TiN)

Step 58. Post CMP clean

Step 59. ILD oxide deposition

Step 60. Contact photo

Step 61. Contact etch

Step 62. Resist strip

Step 63. Aluminum deposition

Step 64. M1 photo

Step 65. Aluminum etch

Step 66. Resist strip and clean

Step 67. Sintering

Last updated: 08/16/2004