Run Card for FlexFET process

Step 24. PSG spacer etch

Steps

Notes

Date

Operator

24.1

PSG spacer etch in Applied Centura:

Recipe: MXP_OXSP_ETCH with automatic endpoint detection

Etch times (recipe endpointed at):

F#3, 7, 11, 13, 14: 25 sec

F#2, 5: 26 sec

F#6, 7, 10, 12: 27 sec

04/20/04

Horvath

24.2

Check the Si surface cleanness by measuring

Si device layer thickness on 1511A BOX (Nanospec):

Wafer (SOI type)	Si device layer thickness
F#2 (Thick, silicided)	1683A
F#3 (thin, implanted)	210A
F#5 (thin, silicided)	1258A
F#6 (thin, silicided)	1266A
F#7 (Thick, implanted)	321A
F#9 (Thick, silicided)	1737A
F#10 (Thick, silicided)	1705A
F#11 (thin, implanted)*	65A*
F#12 (thin, silicided)	1251A
F#13 (Thick, implanted)	400A
F#14 (Thick, implanted)	369A

Note: During the oxide spacer etch we lost ~100A of device Si layer (selectivity)

*: F#11 was sacrificed for Charles Evans analytical SEM cross-section (wafer was sent out on 4/28/04)

04/20/04

Horvath