Run Card for FlexFET process

 

 

Step 40. Bottom gate Si etch         

 

 

 

Steps

Notes

Date

Operator

 

40.1

 

 

Test Centura DPS_SI_ETCH recipe main etch selectivity Si/nitride:

 

For PQECR nitride: ~ 12:1

For LPCVD nitride: ~ 5:1

 

05/28/04

Horvath

 

40.2

 

 

Wafer

Estimated

Si thickness

Etch time

#2

1600A

40 sec

#3

155A

15sec + 15sec OE

#5

1100A

25sec + 15sec OE

#6

1200A

30sec

#7

260A

15sec + 15sec OE

#9

1660A

40sec

#10

1600A

40sec

#12

1200A

30sec + 15sec OE

#13

400A

20sec

#14

350A

15sec + 15 sec OE

 

Overetch needed on some wafers, because Si residue was detected on their BOX surface.

 

05/28/04-

06/01/04

Horvath