Run Card for FlexFET process

 

 

Step 9.0 NMOS photo

 

 

 

Steps

Notes

Date

Operator

9.1

 

Wafers: CMOS implanted S/D wafers only:

F#1, 3, 7, 8.

 

Standard DUV litho step with BARC coating

Exposure energy 45 mJ/cm2, FlexFET2 reticle, mask N SELECT.

Wafers are a little over-exposed (however 0.5um is OK)

Hard bake in oven 120°C for 30 min.

 

12/03/03

Horvath

9.2

 

BARC removal from exposed areas:

Lam4: recipe 6003 (new setup)

 

2-step recipe:

 

1.) Main etch

Press: 425 mTorr

RF power: 300 W

Gap: 1.2 cm

O2: 15 sccm

CHF3: 90 sccm

He: 200 sccm

 

2.) Secondary etch/Residue removal

Press: 425 mTorr

RF power: 200W

Gap: 1.2 cm

O2: 50 sccm

 

Etching time: 40 sec (1st part) + 8 sec (2nd part)

 

100 A SiO2 left on a dummy; assuming the same results on work wafers

 

12/05/03

Horvath/

Parsa