Run Card for FlexFET process

 

 

Step 20a Silicon etch on implanted S/D wafers

 

 

 

Steps

Notes

Date

Operator

20a.1

 

Implanted S/D wafers only:

F# 1, 3, 7, 11, 13, 14.

 

Si trench etch with Applied Centura:

 

Recipe: DPS_SI_ETCH

Etch rate:

40-45A/sec for very short etch time (~10sec)

50-57A/sec for short etch time (~20sec)

 

Wafer (SOI type)

Etch time (sec)

Over etch time (sec)

F#1* (thin)

19*

 

F#3 (thin)

16

5

F#7 (Thick)

23

5

F#11 (thin)

18

5

F#13 (Thick)

16+9

5+5

F#14 (Thick)

22

5

 

* See notes below.

 

03/12/04

Horvath

 

20a.2

 

 

Photoresist removal and cleaning:

 

- Matrix (2.5 min O2 plasma)

- 10 min. NON-MOS piranha clean in sink8

- 10 min. MOS piranha clean in sink8 +

10 sec 10/1 HF dip

 

 

03/12/04

Horvath

 

20a.3

 

 

Measurements after the etching and cleaning:

 

a)     ASIQ profilometer trench depth (measured depth / calculated Si trench depth (measured -1800A, which was the pad nitride thickness))

 

 

 

T

C

F

F#1*(thin)

3530/1730

3440/1640

3550/1750

F#3 (thin)

3060/1260

2870/1070

3000/1200

F#7 (Thick)

3370/1570

3240/1420

3350/1550

F#11 (thin)

3190/1390

3020/1220

3110/1310

F#13 (Thick)

3390/1590

3160/1360

3290/1490

F#14 (Thick)

3380/1580

3150/1350

3270/1470

 

 

 

b)     Nanospec (program 116: Si on 1510Å oxide) remaining Si thickness on large pattern areas:

 

 

 

T

C

F

L

R

F#1*

0

0

0

0

0

F#3

175

297

167

210

170

F#7

260

400

273

314

324

F#11

43

146

45

60

87

F#13

325

477

370

373

335

F#14

322

454

355

350

347

 

Because of the etch behavior, the remaining Si thickness on smaller (0.35-0.5um) pattern areas are approx. 100-150A more than these measured values (~10% etch rate difference).

 

 

 

03/12/04

Horvath

 

* Notes: F#1 was etched previously with an alternative recipe (without HBr) when the

HBr MFC was malfunctioning. This wafer was over etched, and not available for

further processing.