The first baseline CMOS process on 6" wafers

Step 0. (Zero layer photo and etching)

Step 1. (Initial Oxidation)

Step 2. (Nitride Deposition)

Step 3. (N-Well Photo)

Step 4. (Plasma Etch Nitride)

Step 5. (N-Well Implant)

Step 6. (N-Well Cover Oxidation)

Step 7. (Nitride Removal)

Step 8. (P-Well Implant)

Step 9. (Well Drive-in)

Step 10. (Pad Oxidation/Nitride Deposition)

Step 11. (Active Area Photo)

Step 12. (Nitride Etch)

Step 13. (P-Well Field Implant Photo)

Step 14. (P-Well Field Ion Implant)

Step 15. (N-Well Field Implant Photo)

Step 16. (N-Well Field Ion Implant)

Step 17. (Locos Oxidation)

Step 18. (Nitride Removal)

Step 19. (Sacrificial Oxide)

Step 20. (N-Channel Punchthrough and Threshold Adjustment Photo)
Step 21. (N-Channel Punchthrough and Threshold Adjustment Implant. Include NCH)

Step 22. (P-Channel Punchthrough and Threshold Adjustment Photo: Mask PVT)

Step 23. (P-Channel Punchthrough and Threshold Adjustment Implant. Include PCH)

Step 24. (Gate Oxidation/Poly-Si Deposition)

Step 25. (Poly Gate Photo)

Step 26. (Etch poly-Si in lam4)

Step 27. (Reoxidation and Capacitor Formation: no capacitor is requested, skip step 30.)

Step 30. (N+ S/D Photo)

Step 31. (N+ S/D Implant)

Step 32. (N+ S/D Anneal)

Step 33. (P+ S/D Photo)

Step 34. (P+ S/D Implant)

Step 35. (PSG Deposition and Densification)

Step 36. (Contact Photo)

Step 37. (Contact Plasma Etch)

Step 38. (Back Side Etch)

Step 39. (Metallization)

Step 40. (Metal Photo)

Step 41. (Plasma Etch Al/2%Si)

Step 42. (Sintering)

Step 43. (Testing)

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