Run Card for CMOS150

Step 0.0

 

 

 

 

 

 

 

 

Starting wafers

 

Date

operator

 

 

 

 

 

 

 

 

 

 

 

 

1

20-40 ohm-cm, p-type, <100>

17/07/2001

vorosl

 

thickness=675+/-20 micron

 

 

 

Grade: P (prime)

 

 

 

 

size: 6"

 

 

 

 

 

15 wafers + 2 control NCH and PCN

 

 

 

 

 

 

 

 

2

Scribe lot and wafer number on each wafers,

 

 

 

including controls.

 

 

 

 

Piranha clean and dip in sink9.

 

 

 

Measure bulk resistivity (ohm-cm) of each on

 

 

 

SONOGAGE.

 

 

 

 

 

 

 

 

 

 

Note: SONOGAGE is out of order,

 

 

 

THIS STEP WAS SKIPPED!

 

 

 

 

 

 

 

 

3

Zero layer photo (PM marks)

 

 

 

 

 

 

HMDS and coat wafers with SVGCOAT6

17/07/2001

vorosl

 

Program #1 for all station, proximity bake.

 

 

 

 

 

 

 

 

 

Expose using ASML

 

18/07/2001

vorosl

 

job name: baseline, energy=30mJ/cm2

 

 

 

Zero layer reticle

 

 

 

 

 

 

 

 

 

 

Post exposure bake and develop using

Missed out!!!

 

 

SVGDEV6 program #1

 

 

 

 

 

 

 

 

 

Hard bake

 

 

18/07/2001

vorosl

 

 

 

 

 

 

 

Note: Missed out developing, rework Zero layer

 

 

 

 

 

 

 

 

 

Rework:

Ashing PR in MATRIX

19/07/2001

vorosl

 

 

Power 450 W, time 1min. 30sec.

 

 

 

 

 

 

 

 

 

 

Standard clean in SINK9

19/07/2001

vorosl

 

 

Put it in piranha for 10 min. (MEMS side)

 

 

 

 

(add 100 ml H2O2 to it)

 

 

 

 

Rinse (2 cycles)

 

 

 

 

Dip into 10:1 HF until dewet or 1 min.

 

 

 

 

Rinse (2 cycles)

 

 

 

 

Spindryer for 6 inch cassette

 

 

 

 

 

 

 

 

 

Zero layer photo (PM marks)

 

 

 

 

 

 

 

HMDS and coat wafers with SVGCOAT6

20/07/2001

vorosl

 

Program #1 for all station, proximity bake.

 

 

 

 

 

 

 

 

 

Expose using ASML

 

20/07/2001

vorosl

 

job name: baseline, energy=30mJ/cm2

 

 

 

Zero layer reticle, identified by bar code

 

 

 

 

 

 

 

 

 

Post exposure bake (130 C) and develop using

20/07/2001

vorosl

 

SVGDEV6 program #1

 

 

 

 

 

 

 

 

 

Inspect 2 alignment marks on all wafers

 

 

 

Pattern should be white and bright

 

 

 

 

 

 

 

 

 

Hard bake in oven, time more than 30 min.

20/07/2001

vorosl

 

 

 

 

 

 

4

Etch zero layer into the substrate in LAM4

24/07/2001

vorosl

 

Target depth= 1200 A

 

 

 

Recipe= 6000, power 200, time 30 sec

 

 

 

Check the first wafer before proceed

 

 

 

Scribe lot and wafer number on each wafers

 

 

 

 

 

 

 

 

 

Note: Lam4 had exit arm problem on 23/07/2001

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ash photoresist in MATRIX

24/07/2001

vorosl

 

 

 

 

 

 

 

Standard clean of wafers (MEMS)

24/07/2001

fatima

 

 

 

 

 

 

 

Note: wafer #11 has broken during the drying process

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Measure the depth of the alignment marks.

24/07/2001

fatima

 

AS200

 

 

 

 

 

 

depth in [kA]

 

 

 

wafer #

left

right

 

 

 

1

1.3

1.3

 

 

 

2

1.3

1.3

 

 

 

3

1.3

1.3

 

 

 

4

1.3

1.3

 

 

 

5

1.3

1.3

 

 

 

6

1.15

1.15

 

 

 

7

1.2

1.2

 

 

 

8

1.2

1.2

 

 

 

9

1.2

1.2

 

 

 

10

1.2

1.2

 

 

 

11

broken

broken

 

 

 

12

1.3

1.3

 

 

 

13

1.3

1.3

 

 

 

14

1.2

1.2

 

 

 

15

1.2

1.2