CMOS Baseline
General Baseline Information
  • Introduction
  • NanoLab Memoranda
  • Baseline Engineers
    • Baseline Reports
  • Report VIII: 0.35 um CMOS Process on Six-Inch Wafers The First Baseline Run in the New Marvell NanoLab by A. Szucs
  • Report VII: 0.35 um CMOS Process on Six-Inch Wafers by L. Petho
  • Report VI: 0.35 um CMOS Process on Six-Inch Wafers by L. Petho & A. Pongracz
  • Report V: 0.35 um CMOS Process on Six-Inch Wafers by A. Pongracz & G. Vida
  • Report IV: 0.35 um CMOS Process on Six-Inch Wafers by A. Horvath, S. Parsa, H.Y. Wong (pdf)
  • Report III: Six-Inch CMOS Baseline Process by L. Voros, S. Parsa (pdf)
  • Report II: CMOS Baseline Process by L. Voros (pdf)
  • Report I: CMOS Baseline Process by S. Fang (pdf)
    • Four-Inch Runs
  • CMOS 61:  NVt, PVt, Resistivity
  • CMOS 60:  NVt, PVt, Resistivity
  • CMOS 59:  NVt, PVt, Resistivity
  • CMOS 58:  NVt, PVt, Resistivity
    • Six-Inch Runs
  • CMOS 190 (0.35 um)
  • CMOS 180 (0.35 um with Mix&Match and STI)
  • CMOS 170 (advanced 0.35 um)
  • CMOS 161 (0.35 um)
  • CMOS 150 (1.3 um)
    • Graphics
    Process Logs

    07/31/25