Microlab cmos61 Process Log
Begun on Thu Jul 20 08:56:37 PDT 2000 by vorosl@silicon.EECS.Berkeley.EDU

Mask set: CMOS58
Requested by: baseline CMOS
1.0 um, twin-well, double poly, double metal cmos process

Process Log: cmos61
Modified: Thu Jul 20 08:57:24 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 07/14/00

Step Number: 0.0

Step Title: Starting Wafers: 24-36 ohm-cm, p-type, <100>.
__________________________________________________

Procedure: Control wafers: NCH, PCH wafers.
Scribe lot and wafer number on each wafer, including controls.
Piranha clean and dip in sink8.
Measure bulk resistivity (ohm-cm) of each wafers on Sonogage:

Sonogage was down for couple months.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

=============================================================================

Process Log: cmos61
Modified: Thu Jul 20 09:11:57 PDT 2000
---------------------------------------------------

Operator: ernes, vorosl

Date: 07/14/00

Step Number: 1.0

Step Title: Initial oxidation: target= 30(+/-5%) nm
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan5).
2. Standard clean wafers (include NCH, PCH) in sink6:
piranha 10 minutes, 10/1 HF dip, spin-dry.
3. Dry oxidation at 950 C (SGATEOX):
60 min. dry O2
20 min. dry N2
Measure oxide thickness on PCH:
wafer center top left flat right
PCH 308 311 306 307 312

=============================================================================

Process Log: cmos61
Modified: Thu Jul 20 09:20:23 PDT 2000
---------------------------------------------------

Operator: ernes, vorosl

Date: 07/14/00

Step Number: 2.0

Step Title: Nitride Deposition target= 1000 A, include NCH
__________________________________________________

Procedure: Transfer wafers to tylan9 right after the oxidation and
deposit 100 nm nitride. Only include NCH.
Deposition time= 30 minutes
Measure nitride thickness on NCH, Tnit=

wafer center left flat right top
NCH 841 847 839 838 842


=============================================================================

Process Log: cmos61
Modified: Thu Jul 20 09:46:43 PDT 2000
---------------------------------------------------

Operator: ernes

Date: 07/17/00

Step Number: 3.0

Step Title: Well photo: Mask NWELL (CWN chrome-df)
__________________________________________________

Procedure: Standard I-line process.

=============================================================================

Process Log: cmos61
Modified: Thu Jul 20 09:49:36 PDT 2000
---------------------------------------------------

Operator: vorosl, ernes

Date: 07/18/00

Step Number: 4.0

Step Title: Plasma etch nitride in lam1
__________________________________________________

Procedure: Plasma etch nitride in lam1.
Recipe: NITSTD1 Power=150 W
Etch time= 1 min. 15 sec. Overetch=15%
Measure the oxide thickness on each work wafer:

wafer #1 #2 #3 #4 #5 #6 #7 #8 #9 #10
center 279 286 279 265 232 240 257 216 221 272
top 299 320 310 288 263 264 283 233 257 294

=============================================================================

Process Log: cmos61
Modified: Thu Jul 20 10:00:19 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 07/19/00

Step Number: 5.0

Step Title: N-well Implantation, Include PCH
__________________________________________________

Procedure: Phosphorus, 4E12/cm2, 80 KeV.

=============================================================================

Process Log: cmos61
Modified: Wed Aug 2 08:50:22 PDT 2000
---------------------------------------------------

Operator: vorosl, ernes

Date: 07/28/00

Step Number: 6.0

Step Title: N-well Cover Oxidation
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan2).
(since tylan2 was overbooked, we skipped TCA)!
2. Remove PR in O2 plasma (Matrix) and clean wafers in sink8.
3. Standard clean wafers in sink6, include PCH and NCH.
4. Well cover oxidation at 950 C. Recipe: NWELLCVR
30 min. dry O2
175 min. wet O2
30 min. dry O2
30 min. N2

5. Measure the oxide thickness on N-well area:
wafer PCH #1 #3 #5 #7 #9
center 5402 4941 5086 5756 5110 5100
top 5279 4973 5069 5101 5122 5078
flat 5217 4897 4983 5105 5028 5032
left 5236 4940 5001 5115 5078 5046
right 5268 4945 5065 5061 5093 5077


=============================================================================

Process Log: cmos61
Modified: Wed Aug 2 09:16:27 PDT 2000
---------------------------------------------------

Operator: vorosl, ernes

Date: 07/31/00

Step Number: 7.0

Step Title: Nitride Removal
__________________________________________________

Procedure: 1. Dip in 10:1 HF for sec to remove thin oxide on
top of Si3N4.
2. Etch nitride off in boiling phosphoric acid (sink7).
Estimated etch time: at least 2 hours (etch rate~13 A/min)
3. Measure Tox on NCH and work wafers:
wafer NCH #4 #6 #8 #10
flat 247 328 310 311 312
center 254 318 310 311 311

=============================================================================

Process Log: cmos61
Modified: Wed Aug 2 09:30:07 PDT 2000
---------------------------------------------------

Operator: ernes

Date: 07/31/00

Step Number: 8.0

Step Title: P-well Implant
__________________________________________________

Procedure: B11, 3E12/cm2, 80 KeV, include NCH.

=============================================================================

Process Log: cmos61
Modified: Mon Aug 14 15:07:13 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 08/11/00

Step Number: 9.0

Step Title: Well drive-in
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan2).
2. Standard clean wafers in sink8 and sink6, include controls.
3. Well drive at 1120 C (WELLDR):
60 min. temp. ramp from 750 C to 1120 C
240 min. dry O2
300 min. N2
4. Measure oxide thickness on both control wafers
wafer center top flat right left
PCH 6070 5953 5983 5936 6002
NCH 3112 3104 3106 3117 3108

5. Strip off oxide in 5:1 BHF.
Measure sheet resistance on NCH and PCH:
wafer center top flat right left
PCH 565 586 573 592 578
NCH 1373 1371 1400 1400 1420

=============================================================================

Process Log: cmos61
Modified: Mon Oct 23 10:15:06 PDT 2000
---------------------------------------------------

Operator: wangts

Date: 10/16/00

Step Number: 10.0

Step Title: Pad oxidation/ Nitride Deposition:
target= 30(+6) nm SiO2 + 100(+10) nm Si3N4
__________________________________________________

Procedure: Tylan9 was down for 6" upgrading.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
It was the first attempt with the Tystar9.

=============================================================================

Process Log: cmos61
Modified: Mon Oct 23 10:36:23 PDT 2000
---------------------------------------------------

Operator: vorosl, wangts

Date: 10/23/00

Step Number: 10.0

Step Title: Pad Oxidation/ Nitride Deposition:
target= 30(+6) nm SiO2 + 100(+10) nm Si3N4
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan5). Reserve tystar9.
2. Standard clean wafers. Include PCH and NCH.
3. Dry oxidation at 950 C (SGATEOX):
~1 hour dry O2
30 minutes dry N2 anneal.
Measure tox on NCH wafer:
center top left flat right
331 331 334 338 335
4. Deposit 1000 (+100) A of Si3N4 immediately (9SNITE):
deposition time 17.5 min., temp= 800 C.
Measure nitride thickness on PCH.
wafer center top left flat right
PCH 618 615 631 636 632
#10 750

Since the thickness was less than the requirement, we
deposited extra nitride on the existing nitride.
Standard clean wafers in sink6.
additional deposition time=10 min.

Measure nitride thickness on PCH and work wafers:
wafer center top left flat right
PCH 1210 1197 1267 1297 1262
#1 1400 1373 1479 1542 1478
#6 1472 1433 1500 1558 1517
#10 1436 1348 1439 1485 1455

calculated deposition rate=56-70 A/min.

=============================================================================

Process Log: cmos61
Modified: Tue Oct 24 08:02:58 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 10/24/00

Step Number: 11.0

Step Title: Active Area Photo: Mask ACTV (emulsion-clear field)
__________________________________________________

Procedure: Standard I-line process.
Aperture X,Y= 42.5
Focus value/ exposure time= 260/ 1.38 (integrator mode)
#7, #10 reworked f/e= 260/1.8 (time mode)

=============================================================================

Process Log: cmos61
Modified: Fri Oct 27 11:49:05 PDT 2000
---------------------------------------------------

Operator: vorosl, wangts

Date: 10/25/00

Step Number: 12.0

Step Title: Nitride Etch
__________________________________________________

Procedure: Plasma etch nitride in lam1.
Power= 150 W, overetch= 15%
actual etch rate= ~780 A/min.
etch time= 1' 55"
time & endpoint mode, do not etch PCH.
Measure Tox on each work wafer (2 points):
wafer #1 #2 #3 #4 #5 #6 #7 #8 #9 #10
flat 259 278 257 244 232 262 253 236 243 242
right 279 309 284 271 260 296 273 259 273 275

thickness of the PR trp= 950 nm

=============================================================================

Process Log: cmos61
Modified: Fri Oct 27 16:39:19 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 10/27/00

Step Number: 13.0

Step Title: P-Well Field Implant Photo: Mask PFIELD (emulsion-cf)
__________________________________________________

Procedure: Standard I-line process.
Apertura in X,Y= 42.5
f/e= 260/1.8 (time mode)

=============================================================================

Process Log: cmos61
Modified: Fri Oct 27 16:49:08 PDT 2000
---------------------------------------------------

Operator: vorosl

Date: 10/27/00

Step Number: 14.0

Step Title: P-Well Field Ion Implant
__________________________________________________

Procedure: B11, 70 KeV, 1.5E13/cm2

=============================================================================

Process Log: cmos61
Modified: Thu Nov 16 09:09:16 PST 2000
---------------------------------------------------

Operator vorosl, wangts

Date: 11/15/00

Step Number: 15.0

Step Title: N-well Field Ion Implant Photo (NWELL mask)
__________________________________________________

Procedure: 1. Remove PR in oxigen plasma. Matrix (500W,1'30")
2. Clean wafers in sink8.
3. Standard I-line process.


=============================================================================

Process Log: cmos61
Modified: Thu Nov 16 09:10:27 PST 2000
---------------------------------------------------

Operator: vorosl

Date: 11/16/00

Step Number: 16.0

Step Title: N-well Field Ion Implant
__________________________________________________

Procedure: phosporus, 40 KeV, 3E12


=============================================================================


Process Log: cmos61
Modified: Thu Nov 30 08:36:29 PST 2000
---------------------------------------------------

Operator: vorosl, wangts

Date: 11/28/00

Step Number: 17.0

Step Title: Locos Oxidation: target= 650 nm
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan2).
2. Remove PR in plasma 02 (Matrix).
3. Piranha clean wafers in sink8 and sink6.
Dip in BHF 25:1 for 5-10 sec. Include PCH, NCH.
4. Wet oxidation at 950 C (SWETOXB):
5 min. dry O2
4 hours 30 min. wet O2
5 min. dry O2
20 min. N2 annael
5. Measure Tox on 3 work wafers. Tox=
wafer top center flat left right Avg.
#1 6485 6741 6697 6595 6609 6625
#6 6538 6813 6730 6641 6644 6673
#10 6535 6747 6716 6668 6720 6684
=============================================================================

Process Log: cmos61
Modified: Thu Nov 30 08:59:21 PST 2000
---------------------------------------------------

Operator: wangts

Date: 11/29/00

Step Number: 18.0

Step Title: Nitride Removal, include PCH.
__________________________________________________

Procedure: 1. Dip in 10:1 BHF for 60 sec to remove thin oxide on top of Si3N. 2. Etch nitride off in phosphoric acid at 160 C (sink7).
etch rate was ~11 A/min.

=============================================================================

Process Log: cmos61
Modified: Thu Nov 30 09:06:03 PST 2000
---------------------------------------------------

Operator: wangts, vorosl

Date: 11/30/00

Step Number: 19.0

Step Title: Sacrifitial Oxide: target= 20 (+/- 2) nm
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan5).
2. Clean wafers in sink8, include NCH and PCH.
Dip in 10:1 BHF until PCH NCH dewet.
approx. ~1 min. 25 sec. (Handel NCH separetly,
since it has much thicker oxide.)
Field oxide thickness after dip
wafer top center flat left right
#1 5018 5315 5230 5042 5201
#6 5019 5387 5295 5072 5173
#10 5011 5358 5295 5110 5254

3. Dry oxidation at 950 C (SGATEOX):
30 min. dry O2
30 min. N2 anneal
Measure Tox on PCH and NCH. Tox=
wafer flat center top left right
NCH 227 238 235 233 230
PCH 247 246 245 248 244


=============================================================================

Process Log: cmos61
Modified: Thu Nov 30 14:28:26 PST 2000
---------------------------------------------------

Operator: vorosl

Date: 11/30/00

Step Number: 20.0

Step Title: N-Channel Punchthrough and Threshold Adjustment Photo:
Mask PFIELD ( CWNI emulsion-cf).
__________________________________________________

Procedure: Standard I-line process.
Apertura setting: X,Y= 42.5!

=============================================================================

Process Log: cmos61
Modified: Fri Dec 8 10:11:53 PST 2000
---------------------------------------------------

Operator: vorosl, wangts

Date: 12/08/00

Step Number: 22.0

Step Title: P-Channel Punchthrough and Threshold Adjustment Photo: Mask PVT (chrome-df).
__________________________________________________

Procedure: Remove PR in plasma O2 and clean wafers in sink8.
Standard I-line process.

=============================================================================

Process Log: cmos61
Modified: Tue Jan 9 17:17:03 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 12/15/00

Step Number: 23.0

Date: 12/15/01

Step Title: P-Channel Punchthrough and Threshold Adjustment Implant.
Include PCH.
__________________________________________________

Procedure: Phosphorus, 190 KeV, 1E12
B11, 20 KeV, 2.4E12

=============================================================================

Process Log: cmos61
Modified: Tue Jan 9 17:27:34 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 01/08/01

Step Number: 24.0

Step Title: Gate Oxidation/Poly-Si Deposition:
target= 20(+/- 2.0) nm SiO2 + 450(+/- 40) nm poly-Si
__________________________________________________

Procedure: Tystar10 is coming up!
^^^^^^^^^^^^^^^^^^^^^^

=============================================================================

Process Log: cmos61
Modified: Tue Jan 9 17:34:18 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 01/09/01

Step Number: 24.0

Step Title: Gate Oxidation/ Poly-Si Deposition:
target= 20(+/- 2) nm SiO2 + 450(+/- 40) nm poly-Si
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan5).
Reserve poly-Si deposition tube (tystar10).
In this run the wafers were split into 3 groups for
poly-Si deposition.
Wafer#1-3 went into tystar19.
Wafer#4-5 went into tylan16.
Wafer#6-10 went into tystar10.

2. Standard clean wafers, include PCH, NCH,
Tox (prime P<100>), and two Tpoly monitoring wafers.
3. Dip off sacrificial oxide in 10:1 HF until NCH and PCH
dewet (approx. 1 min.).
4. Dry oxidation at 950 C (SGATEOX).
(include NCH, PCH, Tox, Tpoly)
30 min dry O2 (check previous run result)
30 min N2 anneal.
5. immediately after oxidation deposit 450 nm of
phos.doped poly-Si.
Compare the results, wafers were split into 3 groups:


Wafer#1-3
Tystar19: recipe=SIGEVAR.19
SiH4=100 sccm, PH3=2 sccm, time= 3 hours
temperature= 615 C
poly-Si thickness:
wafer center flat top
#1 4710 4977 4623
#2 4642 4846 4643

Wafer#4,5
Tylan16: recipe=16DOPLYB
SiH4=100 sccm, PH3=2 sccm, time= 3 hours 45 min.
temp= 604/610/616 (load/center/pump)
poly-Si thickness:
wafer center top left flat right
Tpoly2 4444 4421 4479 4488 4384
sheet resistance (be aware this value without annealing):
170 172 167 170 172 [ohm/sq.]

Wafer#6-10
Tystar10: recipe=10TDPLYB
150SiH4/9PH3/375mtorr/L620C600S650
deposition time= 150 min.,
poly-Si thickness:
wafer center top left flat right
Tpoly 4878 4879 5031 5169 5022
sheet resistance (be aware this value without annealing):
172 172 168 164 168 [ohm/sq.]
6. Measurements:
a) oxide thickness on Tox, NCH:
wafer center top left flat right
Tox 197 191 187 209 187
NCH 228 224 227 215 196

in case of wafer#1-3 the gate oxide was redone:
wafer center top left flat right
Tox2 205 212 205 215 212
NCH 205 201 199 188 201

b) Measure Dit and Qox on Tox:
Tox Nsc Qox Dit
top 3.42E+14 6.16E+10 1.37E10
right 3.41E+14 6.04E+10 1.47E+10
flat 3.35E+14 5.64E+10 1.6E+10
left 3.27E+14 6.02E+10 1.67E+10
center 3.94E+14 6.31E+10

c) Strip oxide from PCH and NCH, and measure the sheet
resistance. (since we skipped the 2nd poly, we left
the oxide on PCH and NCH)

d) Measure poly thickness on Tpoly1:
See above for the different furnaces.

Tpoly control wafers proceed to step 32.3.




=============================================================================


Process Log: cmos61
Modified: Mon Jan 22 11:40:20 PST 2001
---------------------------------------------------

Operator: vorosl, johnkcp

Date: 01/22/01

Step Number: 25.0

Step Title: Gate Definition: Mask POLY (emulsion-cf)
__________________________________________________

Procedure: Standard I-line process.
Aperture 42.5 in X and Y.
Focus/exposure values= 255/1.5 (integrate mode)
Unexposed dice, due to the "light too low" err.
wafer position (X, Y)
#3 7,6
#4 2,8
#7 9,9
#8 3,5 and 6,9
#9 6,8

=============================================================================

Process Log: cmos61
Modified: Mon Jan 29 11:36:05 PST 2001
---------------------------------------------------

Operator: vorosl, johnkcp

Date: 01/24/01

Step Number: 26.0

Step Title: Plasma Etch Poly-Si.
__________________________________________________

Procedure: 1. Etch poly-Si in Lam5.
power=300/150, calculated etch time=80 sec.
overetch= 20 %, endpoint turned on ~60 sec.
recipe= 5003
2. Measure Tox in S/D area of work wafers:
wafer top center
#2 286 279
291 276
#5 143 146 (this has 18 sec overetch)
152 118
#10 310 266
320 270

3. Measure channel length using 1.0 um gate. CD.
wafer top center flat
#5 1.13 1.17 1.24
#1 1.07 1.22


============================================================================

Process Log: cmos61
Modified: Mon Jan 29 13:35:12 PST 2001
---------------------------------------------------


Operator: vorosl

Date: 1/30/01

Step Number: 30.0

Step Title: N+ S/D Photo: Mask N+S/D (NSD chrome-df)
__________________________________________________

Procedure: There was a lamp change, svgcoat1 & 2 were down.
Had to use PRS300 to remove PR.

=============================================================================

Process Log: cmos61
Modified: Wed Jan 31 14:07:28 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 2/5/01

Step Number: 31.0

Step Title: N+S/D Implant
__________________________________________________

Procedure: Arsenic, 100 KeV, 5E15/cm2, include NCH.

=============================================================================

Process Log: cmos61
Modified: Thu Feb 8 15:00:01 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 2/7/01

Step Number: 32.0

Step Title: N+S/D Anneal
__________________________________________________

Procedure: 1. TCA clean furnace tube (tylan7).
2. remove PR in O2 plasma and pirnaha clean wafers in sink8
(no dip here).
3. Standard clean wafers in sink6, incl. PCH, NCH, Tpoly.
4. Anneal in N2 at 900 C for 30 min. recipe=N2ANNEAL.
5. Strip oxide from NCH, Tpoly.
Measure Rs of N+S/D implant: Rs=
wafer center top right flat left
NCH
Poly

=============================================================================

Process Log: cmos61
Modified: Fri Feb 9 09:55:17 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 2/8/01

Step Number: 33.0

Step Title: P+S/D Photo: Mask P+S/D (PSD emulsion-cf)
__________________________________________________

Procedure: Standard I-line process.
Aperture setting in X,Y= 42.5
F/e=250/1.8 (time mode)

=============================================================================

Process Log: cmos61
Modified: Fri Feb 9 10:01:59 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 9/2/01

Step Number: 34.0

Step Title: P+S/D Implant, include PCH
__________________________________________________

Procedure: B11, 20 KeV, 5E15/cm2, include PCH.

=============================================================================

Process Log: cmos61
Modified: Tue Mar 13 17:41:10 PST 2001
---------------------------------------------------

Operator: vorosl

Date: 03/13/01

Step Number: 35.0

Step Title: PSG Deposition and densification: target= 700 nm
__________________________________________________

Procedure: 1. Remove PR in O2 plasma (matrix) and clean wafers in sink8
(no dip).
2. Standard clean wafers in sink6 (10 sec dip; 10:1 HF).
Include one PSG monitor wafer and PCH wafer.
3. Deposit 700 nm PSG (tystar11), (reserve tylan2 for dens.)
recipe= 11SDLTOA, (PH3 flow 25 sccm)
temperature= 450 C
time= 43 min. (check current dep.rate)
include PSG control
4. Densify glass in tylan2 at 900 C, immediately after
PSG deposition. Include PSG control and PCH wafers.
recipe= PSGDENS 5 min dry O2
20 min wet O2
5 min dry O2

Measure tPSG (using PSG control and on working wafers
S/D region):
wafer top flat center left right
PSG c.
#1 7887 8120 7948 7967 7910
#2 7752 7832 7729 7931 7723

5. Do wet oxidation dummy run afterwards to clean tube:
1 hour wet oxidation at 950 C (SWETOXB).

=============================================================================

Process Log: cmos61
Modified: Thu Mar 15 09:17:52 PST 2001
---------------------------------------------------

Operator: vorosl, johnkcp

Date: 03/20/01

Step Number: 36.0

Step Title: Contact Photo: Mask CONT (chrome-df)
__________________________________________________

Procedure: Standard I-line process.

=============================================================================

Process Log: cmos61
Modified: Mon Apr 2 14:51:08 PDT 2001
---------------------------------------------------

Operator: vorosl, johnkcp

Date: 03/22/01

Step Number: 37.0

Step Title: Contact Plasma Etch in Lam2.
__________________________________________________

Procedure: Recipe=SiO2ETCH, Power: 850 W, etch time: ?
overetch=?

=============================================================================

Process Log: cmos61
Modified: Mon Apr 2 15:04:29 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 04/02/01

Step Number: 38.0

Step Title: Back side etch
__________________________________________________

Procedure: 1. Remove PR in O2 plasma, piranha clean wafers in sink8
(no dip). Dehydrate wafers in oven at 120 C for > 30 min.
2. Spin PR on front side, hard bake.
3. Dip off oxide (PSG) in 5:1 BHF.
4. Etch poly-Si (poly1 thickness) in Lam5.
5. Final dip in BHF until back dewets.
6. Remove PR in PRS3000, piranha clean wafers in sink8 (no dip).



=============================================================================

Process Log: cmos61
Modified: Wed Apr 18 13:50:21 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 04/18/01

Step Number: 39.0

Step Title: Metallization
__________________________________________________

Procedure: cpa is down for Al/Si target.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

=============================================================================

Process Log: cmos61
Modified: Fri May 18 16:50:34 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 05/09/01

Step Number: 39.0

Step Title: Metallization: target= 600nm
__________________________________________________

Procedure: 1. Standard clean wafers and 10 sec 5:1 BHF dip just before
metallization.
2. Sputter Al/2%Si on all wafers in CPA.
pressure= 6mtorr, 5KW, track speed 20 cm/min, 2 passes


=============================================================================

Process Log: cmos61
Modified: Mon Jul 2 15:34:34 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 5/11/01

Step Number: 40.0

Step Title: Metal Photo: Mask METAL1 CMF (emulsion-cf)
__________________________________________________

Procedure: Standard I-line process.
-baseline correction for GCAWS.
-focus value/ exposure time[sec.]= 248/4
-offset for the alignment marks

=============================================================================

Process Log: cmos61
Modified: Mon Jul 2 15:44:57 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 5/11/01

Step Number: 41.0

Step Title: Plasma etch Al in Lam3.
__________________________________________________

Procedure: 1. Etch Al/2%Si in lam3.
Etch time=1:30 power=250 W, overetch=50%
2. Pemove PR in matrix. tAl=900nm
3. Probe test devices with iv.

=============================================================================

Process Log: cmos61
Modified: Mon Jul 2 15:57:04 PDT 2001
---------------------------------------------------

Operator: vorosl

Date: 5/13/01

Step Number: 42.0

Step Title: Sintering: 400 C for 20 min in forming gas.
__________________________________________________

Procedure: 1. Clean wafers in sink8, no HF.
2. Use tylan13, no ramping, recipe: SINT400

=============================================================================

Process Log: cmos61
Modified: Mon Jul 2 16:25:46 PDT 2001
---------------------------------------------------

Operator: vorosl, fatima

Date: 5/15/01

Step Number: 43.0

Step Title: Testing.
__________________________________________________

Procedure: Both NMOS and PMOS transistors work well.
Details on the Baseline's website: