Microlab
cmos58 Process Log
Begun on Wed Oct 14 10:55:52 PDT 1998 by
gwang@palladium.eecs.berkeley.edu
Mask set: CMOS58
Requested by: baseline CMOS
1.0um,twin-well, double metal cmos process.
Process Log: cmos58
Modified: Wed Oct 14 10:56:12 PDT 1998
---------------------------------------------------
Operator: gwang
Date: 10/14/98
Step Number: 0.0
Step Title: Starting Wafers: 24-36
ohm-cm, p-type, <100>.
__________________________________________________
Procedure: Control wafers: NCH, PCH
wafers.
Scribe lot and wafer number
on each wafer, including controls.
Piranha clean and dip in
sink8.
Measure bulk
resistivity(ohms-cm) of control wafer on Sonogage:
wafer ID
center top left flat
right
NCH 28.6
27.4 25.4 28.5
26.9
PCH 27.7
26.6 27.3 28.1
27.1
=============================================================================
Process Log: cmos58
Modified: Thu Oct 15 13:24:48 PDT 1998
---------------------------------------------------
Operator: gwang & kjlewis
Date: 10/15/98
Step Number: 1.0
Step Title: Initial Oxidation: target = 30 (+/- 5%) nm
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan5).
2. Standard clean wafers in
sink6:
piranha 10 minutes, 10/1
HF dip, spin-dry.
3. Dry oxidation at 950 C
(SGATEOX):
60 min. dry O2
20 min. dry N2
check the Tox on PCH:
wafer center
top left flat
right S.D.
PCH 299
298 294 295
301 298/2
=============================================================================
Process Log: cmos58
Modified: Thu Oct 15 13:26:55 PDT 1998
---------------------------------------------------
Operator: gwang & kjlewis
Date: 10/15/98
Step Number: 2.0
Step Title: Nitride Deposition target=1000 A, include NCH
__________________________________________________
Procedure: Transfer wafers to tylan9
right after 1.3 and deposit 100nm Nit.
Deposit time = 21 min.
Check the thickness of
nitride on NCH:
wafer center
top left flat
right S.D.
NCH 869
875 874 876
879 875/4
=============================================================================
Process Log: cmos58
Modified: Wed Oct 21 12:43:36 PDT 1998
---------------------------------------------------
Operator: kjlewis
Date: 10/20/98
Step Number: 3.0
Step Title: Well Photo: Mask NWELL
(chrome-df)
__________________________________________________
Procedure: Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Wed Oct 21 12:47:42 PDT 1998
---------------------------------------------------
Operator: gwang
Date: 10/20/98
Step Number: 4.0
Step Title: plasma etch nitride in lam1
__________________________________________________
Procedure: lam1 was down from
10/15/98.
=============================================================================
Process Log: cmos58
Modified: Mon Oct 26 10:19:38 PST 1998
---------------------------------------------------
Operator: gwang
Date: 10/26/98
Step Number: 4.0
Step Title: plasma etch nitride in lam1
__________________________________________________
Procedure: Plasma etch nitride in
lam1.
Recipe: NITSTD1 Power= 150 W
Etchtime= 1'10" Overetch= 15%
Measure the oxide
thickness on each work wafer:
wafer #1
#2 #3 #4
#5 #6 #7
#8 #9 #10
center 202
216 209 180
204 204 196
211 211 199
top 206
201 216 194
217 198 197
223 231 216
=============================================================================
Process Log: cmos58
Modified: Mon Oct 26 10:22:43 PST 1998
---------------------------------------------------
Operator: gwang
Date: 10/26/98
Step Number: 5.0
Step Title: N-well Implantation,
Include PCH.
__________________________________________________
Procedure: Phosphorus, 4E12/cm2, 80
KeV.
=============================================================================
Process Log: cmos58
Modified: Mon Nov
9 10:41:26 PST 1998
---------------------------------------------------
Operator: gwang
Date: 10/30/98
Step Number: 6.0
Step Title: N-well Cover Oxidation
__________________________________________________
Procedure: 1. TCA clean furnace tube (tylan2).
2. Remove PR in O2 plasma
and clean wafers in sink8.
3. Standard clean wafers in
sink6, include NWELL and PWELL.
4. Well cover oxidation at
950: (NWELLCVR)
30 min. dry O2
175 min. wet O2
30 min. dry O2
20 min. N2
wafer PCH
#2 #4 #6
#10
center
4916 4871 4846
4829 4865
top 4896
4869 4840 4825
4857
left 4886
4870 4847 4828
4860
flat 4892
4884 4854 4842
4874
right 4901
4879 4847 4837
4873
=============================================================================
Process Log: cmos58
Modified: Mon Nov
9 10:46:03 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/2/98
Step Number: 7.0
Step Title: Nitride Removal
__________________________________________________
Procedure: 1. Dip in 10:1 HF for 40 sec to remove thin
oxide on top
of Si3N4.
2. Etch nitride off in
boiling phosphoric acid (sink7).
measure Tox on NCH and work
wafers:
wafer center
top left flat
right
NCH 203
208 210 211
209
=============================================================================
Process Log: cmos58
Modified: Mon Nov
9 10:48:29 PST 1998
---------------------------------------------------
Operator: kjlewis
Date: 11/03/98
Step Number: 8.0
Step Title: P-Well Implant
__________________________________________________
Procedure: B11, 3E12/cm2, 80KeV,
include NCH.
=============================================================================
Process Log: cmos58
Modified: Mon Nov
9 10:49:13 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/06/98
Step Number: 9.0
Step Title: Well Drive-In
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan2).
2. Standard clean wafers in
sink8 and sink6, include controls
3. Well drive at 1120 C
(WELLDR):
1 hr. temp. ramp from
750 C to 1120 C
4 hrs. dry O2
5 hrs. N2
Measure oxide thickness
on two control wafers
center top
left flat right
PCH 5902
5885 5869 5875
5891
NCH 3075
3079 3074 3083
3085
4. Strip oxide in 5:1
HF.
Measure Rs on NCH and
PCH:
center top
left flat right
NCH 533
524 514 523
508
PCH 1491
1501 1508 1507
1485
=============================================================================
Process Log: cmos58
Modified: Tue Nov 10 15:12:46 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/10/98
Step Number: 10.0
Step Title: Pad Oxidation/Nitride
Deposition:
target = 30 (+6) nm SiO2
+ 100 (+10) nm Si3N4
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan5). Reserve tylan9.
2. Standard clean
wafers. Include PCH and NCH.
3. Dry oxidation at 950 C
(SGATEOX):
~1 hr. dry O2
30 minutes dry N2
anneal.
Measure tox on
monitoring wafers. Tox=
wafer center
top left flat
right STD
NCH 307
304 300 303
300 303/3
4. Deposit 1000 (+100) A of
Si3N4 immediately (SNITC):
time = 24 min., temp.=
800 C.
Measure nitride thickness
on PCH.
wafer center
top left flat
right STD
PCH 983
986 986 988
992 987/3
=============================================================================
Process Log: cmos58
Modified: Thu Nov 12 10:41:36 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/11.98
Step Number: 11.0
Step Title: Active Area Photo: Mask ACTV (ACTV emulsion-cf)
__________________________________________________
Procedure: Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Thu Nov 12 10:45:18 PST 1998
---------------------------------------------------
Operator: kjlewis
Date: 11/12/98
Step Number: 12.0
Step Title: Nitride Etch
__________________________________________________
Procedure: Plasma etch in lam1: pw=150; overetch=15%
Etch time=1'10"
Measure Tox on each work
wafer:
wafer #1
#2 #3 #4
#5 #6 #7
#8 #9 #10
center 228
264 216 216
255 219 250
226 186 253
top 238
274 223 228
265 237 252
256 217 266
left 246
269 236 245
265 233 249
243 198 264
flat 237
270 229 244
258 237 259
236 203 267
right 239
278 225 234
262 238 261
237 202 258
tpr=840nm
=============================================================================
Process Log: cmos58
Modified: Fri Nov 20 11:38:57 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/16/98
Step Number: 13.0
Step Title: P-Well Field Implant
Photo: Mask PFIELD (emulsion-cf)
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Fri Nov 20 11:41:59 PST 1998
---------------------------------------------------
Operator: gwang
Date: 11/17/98
Step Number: 14.0
Step Title: P-Well Field Ion Implant
__________________________________________________
Procedure: B11, 70 KeV,
1.5E13/cm2
=============================================================================
Process Log: cmos58
Modified: Mon Nov 23 15:00:37 PST 1998
---------------------------------------------------
Operator: kjlewis
Date: 11/20/98
Step Number: 15.0
Step Title: N-Well Field Implant Photo:
Mask NWELL (CWN chrome-df)
__________________________________________________
Procedure: 1. Remove PR in O2
plasma. Clean wafers in sink8.
2. Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Mon Nov 23 15:04:33 PST 1998
---------------------------------------------------
Operator: kjlewis
Date: 11/23/98
Step Number: 16.0
Step Title: N-well Field Implant
__________________________________________________
Procedure: phosphorus, 40KeV,
3E12
=============================================================================
Process Log: cmos58
Modified: Fri Dec
4 15:48:37 PST 1998
---------------------------------------------------
Operator: gwang & kjlewis
Date: 12/03/98
Step Number: 17.0
Step Title: Locos Oxidation: target =
6500 A
__________________________________________________
Procedure: Tylan2 was down for one
week. Have to use tylan1.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1. TCA clean tylan1.
2. Remove PR in O2 plasma
and piranha clean wafers.
Standard clean wafers;
dip in BHF 25:1 for 5-10 sec.
Include NCH and
PCH.
3. Wet oxidation at 950 C
(SWETOXB):
5 min. dry O2
4 hrs. 40 min. wet
O2
5 min. dry O2
20 min. N2
anneal
Measured tox on 3 work
wafers. Tox=
wafer center
top left flat
right
PCH 6648
6589 6649 6679
6638
=============================================================================
Process Log: cmos58
Modified: Fri Dec
4 15:53:51 PST 1998
---------------------------------------------------
Operator: gwang & kjlewis
Date: 12/04/98
Step Number: 18.0
Step Title: Nitride Removal
__________________________________________________
Procedure: 1. Dip in 5:1 BHF for 30
sec to remove thin oxide on top of Si3N.
2. Etch nitride off in
phosphoric acid at 145 C (sink7).
=============================================================================
Process Log: cmos58
Modified: Mon Dec
7 13:29:15 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/07/98
Step Number: 19.0
Step Title: Sacrificial Oxide: target =
200 (+/-20) A
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan5).
2. Standard clean wafers,
include PCH and NCH.
Dip in 10:1 HF until NCH
and PCH dewet.
Dip time =
1'00"
3. Dry oxidation at 950 C
(SGATEOX):
30 min. dry O2
30 min. dry N2
anneal
Measure Tox on PCH and
NCH:
wafer center
top left flat
right
PCH 193
193 197 195
192
NCH 190
190 189 192
191
=============================================================================
Process Log: cmos58
Modified: Tue Dec
8 16:46:46 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/08/98
Step Number: 20.0
Step Title: N-Channel Punchthrough and
Threshold Adjustment Photo:
Mask PFIELD (CWNI
emulsion-cf)
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Tue Dec
8 16:48:42 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/08/98
Step Number: 21.0
Step Title: N-Channel Punchthrough and
Threshold Adjustment Implant
Include NCH.
__________________________________________________
Procedure: 1. B11, 120KeV,
8E11/cm2.
2. B11, 30KeV, 1.9E12/cm2.
=============================================================================
Process Log: cmos58
Modified: Tue Dec 22 16:21:44 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/12/98
Step Number: 22.0
Step Title: P-Channel Punchthrough and
Threshold Adjustment Photo Mask
Mask: PVT chrome-df
__________________________________________________
Procedure: 1) Remove PR in plasma O2 and clean wafers in
sink8.
2) Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Tue Dec 22 16:23:18 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/13/98
Step Number: 23.0
Step Title: P-Channel Punchthrough and
Threshold Adjustment Implant
Include PCH.
__________________________________________________
Procedure: 1) Phosphorus, 190 KeV, 1E12
2) B11, 20KeV, 2.4E12
=============================================================================
Process Log: cmos58
Modified: Tue Dec 22 16:25:01 PST 1998
---------------------------------------------------
Operator: gwang
Date: 12/23/98
Step Number: 24.0
Step Title: Gate Oxidation/Poly-Si
Deposition:
target = 20(+/-2.0)nm SiO2
+ 450(+/-40)nm poly-Si
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan5), reserve tylan11.
2. Standard clean wafers,
including PCH, NCH and,
Tox and one Tpoly1
monitoring wafers.
3. Dip off sacrificial
oxide in 10/1 HF
until PCH and NCH dewet
(time=1'00").
4. Dry oxidation at 950 C
(SGATEOX):
30 min. dry O2
30 min. dry N2
anneal.
5. Immediately deposit 4500
A of phos.doped poly-Si after
oxidation
(11DOPLYH).
approx.time = 2 hrs 40
min., temp = 610 C
6. a) Measure Tox on
monitoring wafer:
wafers center
top left flat
right
NCH 220 221
222 221 223
Tox 222 224
228 224 223
b) Measure Dit and Qox on
Tox:
wafers Nsc
Qox Dit IQF
Tox 5.92E14 2.89E11
2.13E10 0.93
c) Measure Tpoly:
center top
left flat right
4000 3991
3961 4038 4046
=============================================================================
Process Log: cmos58
Modified: Fri Jan
8 11:25:16 PST 1999
---------------------------------------------------
Operator: gwang
Date: 01/06/99
Step Number: 24.0
Step Title: Gate Definition: Mask POLY
(emulsion-cf)
__________________________________________________
Procedure: GCAWS was down for three
days.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Fri Jan
8 11:29:35 PST 1999
---------------------------------------------------
Operator: gwang
Date: 01/08/99
Step Number: 26.0
Step Title: Plasma etch poly-Si
__________________________________________________
Procedure: Lam5 was down for pipe
change, leakage, ... (3 weeks).
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
=============================================================================
Process Log: cmos58
Modified: Mon Feb
1 11:36:01 PST 1999
---------------------------------------------------
Operator: gwang
Date: 01/29/99
Step Number: 26.0
Step Title: Plasma etch poly-Si
__________________________________________________
Procedure: 1. Etch poly in lam5.
etch time = 45", overetch
= 20% (no endpoint).
2. Measure Tox on S/D
area:
Wafer# 1
2 4 5
6 7 8
9 10
center 203
197 203 216
154 206 201
204 201
edge 212
187 203 219
162 207 201 210 203
3. Measure channel length
using 1.0 um gate:
Wafer # #1
#6 #8
Center(1) 1.28
1.23 1.32
Center(2) 1.12
1.05 1.13
Top(1) 1.2
1.19 1.26
Top(2) 1.1
1.11 1.18
Center Avg
Top Avg
=============================================================================
Process Log: cmos58
Modified: Mon Feb
8 13:08:46 PST 1999
---------------------------------------------------
Operator: kjlewis
Date: 2-2-99
Step Number: 30.0
Step Title: N+ S/D Photo:
Mask N+ S/D (NSD chrome-df)
__________________________________________________
Procedure: Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Mon Feb
8 13:15:51 PST 1999
---------------------------------------------------
Operator: kjlewis
Date: 2-3-99
Step Number: 31.0
Step Title: N+ S/D Implant
__________________________________________________
Procedure: Arsenic, 100 KeV, 5e15/cm2, include NCH.
=============================================================================
Process Log: cmos58
Modified: Fri Feb 12 08:55:11 PST 1999
---------------------------------------------------
Operator: gwang
Date: 2/10/99
Step Number: 32.0
Step Title: N+S/D anneal
__________________________________________________
Procedure: 1. TCA clean furnace tube
(tylan 7)
2. Remove PR in O2 plasma
at 100w for 10 min
Strip off PR in
spindryer3
Put the wafers in PR2000
for 2hrs
3. Standard clean wafers in
sink8 and sink6, include NCH and PCH
4. Anneal in N2 at 900C for
30 min (N2ANNEAL)
5. Measurement:
Rs(NCH)=
center top
left flat right
52.8 52.7
52.1 52.9 52.8
Rs(tpoly1)=
16.9 16.8
16.3 16.5 16.8
=============================================================================
Process Log: cmos58
Modified: Fri Feb 12 08:59:19 PST 1999
---------------------------------------------------
Operator: gwang
Date: 2/11/98
Step Number: 33.0
Step Title: P+S/D Photo
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Fri Feb 12 09:00:05 PST 1999
---------------------------------------------------
Operator: gwang
Date: 2/11/98
Step Number: 34.0
Step Title: P + S/D Implantation
__________________________________________________
Procedure: B11, 20KeV, 5E15/cm2
=============================================================================
Process Log: cmos58
Modified: Fri Feb 19 14:41:44 PST 1999
---------------------------------------------------
Operator: gwang
Date: 02/17/99
Step Number: 35.0
Step Title: PSG Deposition and
Densification
__________________________________________________
Procedure: Tylan12 was down for PH3
used up, calibration ...!
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
=============================================================================
Process Log: cmos58
Modified: Thu Feb 25 14:45:04 PST 1999
---------------------------------------------------
Operator: gwang
Date: 02/24/99
Step Number: 35.0
Step Title: PSG Deposition and
Densification
__________________________________________________
Procedure: 1. Descum PR in O2 plasma
at 50 w for 10min
2. Remove PR in Spoindryer3
and PS3000 tank for several hours.
3. Standard clean wafers in
sink8 (no dip).
4. Standard clean wafers in
sink6 (10 sec dip in 10:1 HF).
Include PSG control
wafers.
5. Deposit 7000A PSG in
tylan 12:
PH3 flow: 5.0 sccm
Recipe: SDOLTOD
Time: 27 min
Temp: 450 C
6. Densify glass in tylan2
at 900 C immediately after PSG
deposition. Include PSG
control wafers
Recipe: PSGDENS
5 min dry O2
20 min wet O2
5 min dry O2
7. Measure PSG thickness on
control wafers:
Center Top
Left Flat Right
5205 5370
5257 5130 5187
8. Measure sheet
resistivity on PCH:
(Strip off oxide on PCH
in sink8)
Wafer Center
Top Left Flat
Right
PCH 122.4
122.6 123.0 123.7
122.8
=============================================================================
Process Log: cmos58
Modified: Thu Feb 25 14:50:41 PST 1999
---------------------------------------------------
Operator: gwang
Date: 02/25/99
Step Number: 36.0
Step Title: Contact Photo: Mask CONT
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Fri Feb
26 16:50:46 PST 1999
---------------------------------------------------
Operator: gwang
Date: 02/26/99
Step Number: 37.0
Step Title: Contact Plasma Etch in
lam2
__________________________________________________
Procedure: Lam2 was down for extremely
lower etch rate.
Lam2 up for use today
(04/14/99)!
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
=============================================================================
Process Log: cmos58
Modified:
Thu Apr 15 10:37:07 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 04/14/99
Step Number: 37.0
Step Title: Contact Plasma Etch in lam2
__________________________________________________
Procedure: 1. Etch contact hole in
Lam2 (SiO2etch):
pwr=850, Etch
time=50", overEtch=20"(pwr=750)
2. Measured oxide after
etch on S/D:
all wafers are less than
100A
3. Dip in 5:1 HF for 10
sec.
=============================================================================
Process Log: cmos58
Modified: Thu Apr 15 10:39:34 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 04/15/99
Step Number: 39.0
Step Title: Metallization: target =
6000A
__________________________________________________
Procedure: 1. Strip off PR in O2
plasma
2. Clean wafers and 30 sec.
25:1 HF dip
before
metallization.
3. Sputter Al/2% Si on all
wafers in CPA.
speed = 25 cm/min.
=============================================================================
Process Log: cmos58
Modified: Thu Apr 15 10:41:05 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 04/15/99
Step Number: 40.0
Step Title: Metal Photo: Mask METAL1-CM
(emulsion-cf)
__________________________________________________
Procedure: Standard I-line process.
=============================================================================
Process Log: cmos58
Modified: Thu Apr 16 10:36:22 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 04/16/99
Step Number: 41.0
Step Title: Plasma etch Al in Lam3
__________________________________________________
Procedure: Lam3 was down for
transportation and etch problems.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
=============================================================================
Process Log: cmos58
Modified: Thu May
6 10:39:19 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/05/99
Step Number: 41.0
Step Title: Plasma etch Al in Lam3
__________________________________________________
Procedure: etch time =
1'10", overetch = 50%.
=============================================================================
Process Log: cmos58
Modified: Thu May
6 10:40:17 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/06/99
Step Number: 42.0
Step Title: Sintering: 400 C for 20min
in forming gas (tylan13)
__________________________________________________
Procedure: No ramping, use SINT400
recipe.
=============================================================================
Process Log: cmos58
Modified: Thu May
6 10:41:36 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/06/99
Step Number: 43.0
Step Title: Testing
__________________________________________________
Procedure: Both p- and n- type
transistors works perfect.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 10:43:03 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/17/99
Step Number: 44.0
Step Title: Planerization and
Dielectric Film Deposition
(divided into two groups,
one group: #2, #5, #6, and #8
continue the following
sencond metal process; another
group: rest of the wafers
may go to the CMP process
later)
__________________________________________________
Procedure: 1. PECVD thin oxide in
technics-B:
N2O:54.0, Silane:14.0,
Pwr:15w, Pressure: 360-420 mT.
~2 min and then rotate
180 degree for ~2 min.
Measure Tox and index on
dummy wafers:
center top
left flat right
748 649 731
707 735
mean/std = 714/39
2. SOG coating on the
Headway spinner at 3000 rpm for 30 sec.
3. SOG cure:
a. Oven in Y2, 120 C, 30
min.
c. Tylan 14 (SOGO2): 400
C, 30min
d. Measure Tox and
refractive index on dummy wafer:
Center Top Left Flat Right
5736/1.43 5547/1.42
5559/1.43 5684/1.43 5630/1.43
4. ECR thick oxide (5000
A): time = 760 Sec.
Measure Tox and refractive index on dummy
wafer:
center top left flat right
10296/1.50 9739/1.50
9948/1.50 10071/1.49 10215/1.50
=============================================================================
Process Log: cmos58
Modified: Thu May 20 10:55:16 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/18/99
Step Number: 45.0
Step Title: VIA photo
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 10:56:13 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/19/99
Step Number: 46.0
Step Title: Etch VIA in lam2
__________________________________________________
Procedure: etch time = 2'40",
overetch = 20".
=============================================================================
Process Log: cmos58
Modified: Thu May 20 11:00:05 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/20/99
Step Number: 47.0
Step Title: Metal2 metalization. target
= 8000-9000 A
__________________________________________________
Procedure: Remove PR in technics-c.
Rinse the wafers in
sink7 and spin dry.
Sputter Al/2% Si on all wafers in CPA ( 3 passes).
speed = 25 cm/min.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 11:01:20 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/21/99
Step Number: 48.0
Step Title: Metal2 Photo: Mask
METAL2-CM (emulsion-cf)
__________________________________________________
Procedure: Standard I-line
process.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 11:02:06 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/24/99
Step Number: 49.0
Step Title: Plasma etch Al in Lam3
__________________________________________________
Procedure: etch time = 1'30",
overetch = 50%.
Remove PR by using
spindryer3 and sink5.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 11:03:56 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/24/99
Step Number: 50.0
Step Title: Sintering: 400C for 20 min.
in forming gas (tylan13)
__________________________________________________
Procedure: No ramping, use SINT400
recipe.
=============================================================================
Process Log: cmos58
Modified: Thu May 20 11:05:42 PDT 1999
---------------------------------------------------
Operator: gwang
Date: 05/25/99
Step Number: 51.0
Step Title: Testing
__________________________________________________
Procedure:
==================== cmos56-4 ======================
******************************************************
***Sheet Resistance Summary************
Name: scbrp+, Mean: 167.417, Std Dev: 4.4875
Name: scbrn+, Mean: 370.471, Std Dev: 69.848
Name: scbrPO, Mean: 31.8893, Std Dev: 0.466816
***Contact Resistance Summary************
Name: conrp+, Mean: 39.89, Std Dev: 0.639024
Name: conrn+, Mean: 40.937, Std Dev: 3.05722
Name: conrpo, Mean: NaN, Std Dev: NaN
*************************************************************
************ Transistor: Mp10x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:7
No catastrophic failure :
69
Short on Gate : 3
Short on Body : 2
Open on Body : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: -0.741341 stddev: 0.0609233
*************************************************************
************ Transistor: Mp5x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:15
No catastrophic failure : 61
Open on Body :
15
***** Threshold Voltage:
VBS: 0 NoTrn: 61 mean: -0.663721 stddev: 0.0728649
*************************************************************
************ Transistor: Mp15x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 59 mean: -0.782298 stddev: 0.02905
*************************************************************
************ Transistor: Mp10x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Open on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: -0.827511 stddev: 0.0294525
*************************************************************
************ Transistor: Mp5x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.78496 stddev: 0.0527202
*************************************************************
************ Transistor: Mp15x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure : 76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.84286 stddev: 0.0202448
*************************************************************
************ Transistor: Mp5x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.863309 stddev: 0.029872
*************************************************************
************ Transistor: Mp10x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.874208 stddev: 0.017788
*************************************************************
************ Transistor: Mp15x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.87602 stddev: 0.0149868
*************************************************************
************ Transistor: Mp5x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.889525 stddev: 0.024267
*************************************************************
************ Transistor: Mp10x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.894079 stddev: 0.0184671
*************************************************************
************ Transistor: Mp15x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure : 76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.892108 stddev: 0.0143773
*************************************************************
************ Transistor: Mp5x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.907191 stddev: 0.0244112
*************************************************************
************ Transistor: Mp10x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.904159 stddev: 0.0185742
*************************************************************
************ Transistor: Mp15x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.902336 stddev: 0.0153386
*************************************************************
************ Transistor: Mp10x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.938521 stddev: 0.0193744
*************************************************************
************ Transistor: Mp5x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.960191 stddev: 0.0263742
*************************************************************
************ Transistor: Mp15x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.932189 stddev: 0.0150073
*************************************************************
************ Transistor: Mp10x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 64 mean: -0.941981 stddev: 0.0185649
*************************************************************
************ Transistor: Mp5x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.965422 stddev: 0.0256844
*************************************************************
************ Transistor: Mp15x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.93454 stddev: 0.0143525
*************************************************************
************ Transistor: Mp5x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.962064 stddev: 0.0253052
*************************************************************
************ Transistor: Mp10x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.938506 stddev: 0.0171566
*************************************************************
************ Transistor: Mp15x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 54 mean: -0.931552 stddev: 0.014445
*************************************************************
************ Transistor: Mn10x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:17
No catastrophic failure : 59
Short on Gate :
17
***** Threshold Voltage:
VBS: 0 NoTrn: 59 mean: 0.73682 stddev: 0.0200251
*************************************************************
************ Transistor: Mn5x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:5
No catastrophic failure :
71
Short on Gate : 4
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 71 mean: 0.721284 stddev: 0.0340931
*************************************************************
************ Transistor: Mn15x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:11
No catastrophic failure :
65
Short on Gate :
11
***** Threshold Voltage:
VBS: 0 NoTrn: 65 mean: 0.740343 stddev: 0.0183122
*************************************************************
************ Transistor: Mn10x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:8
No catastrophic failure :
68
Short on Gate : 7
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 67 mean: 0.746686 stddev: 0.0183093
*************************************************************
************ Transistor: Mn5x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:6
No catastrophic failure :
70
Short on Gate : 6
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: 0.744104 stddev: 0.0261439
*************************************************************
************ Transistor: Mn15x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:8
No catastrophic failure :
68
Short on Gate : 7
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 68 mean: 0.747864 stddev: 0.0163549
*************************************************************
************ Transistor: Mn5x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure : 73
Short on Gate : 3
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: 0.744287 stddev: 0.0730245
*************************************************************
************ Transistor: Mn10x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:11
No catastrophic failure :
65
Short on Gate :
11
***** Threshold Voltage:
VBS: 0 NoTrn: 65 mean: 0.751292 stddev: 0.0158954
*************************************************************
************ Transistor: Mn15x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:7
No catastrophic failure :
69
Short on Gate : 7
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: 0.748014 stddev: 0.016165
*************************************************************
************ Transistor: Mn5x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure :
73
Short on Gate : 3
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: 0.753253 stddev: 0.0226816
*************************************************************
************ Transistor: Mn10x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:13
No catastrophic failure : 63
Short on Gate :
13
***** Threshold Voltage:
VBS: 0 NoTrn: 63 mean: 0.751851 stddev: 0.0158148
*************************************************************
************ Transistor: Mn15x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:7
No catastrophic failure :
69
Short on Gate : 7
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: 0.747764 stddev: 0.0152838
*************************************************************
************ Transistor: Mn5x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:5
No catastrophic failure :
71
Short on Gate : 5
***** Threshold Voltage:
VBS: 0 NoTrn: 71 mean: 0.753508 stddev: 0.0214132
*************************************************************
************ Transistor: Mn10x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:6
No catastrophic failure :
70
Short on Gate : 6
***** Threshold Voltage:
VBS: 0 NoTrn: 70 mean: 0.749782 stddev: 0.0153609
*************************************************************
************ Transistor: Mn15x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:6
No catastrophic failure : 70
Short on Gate : 6
***** Threshold Voltage:
VBS: 0 NoTrn: 70 mean: 0.747206 stddev: 0.0158969
*************************************************************
************ Transistor: Mn10x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure :
73
Short on Gate : 3
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: 0.742169 stddev: 0.0138777
*************************************************************
************ Transistor: Mn5x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.748405 stddev: 0.0182524
*************************************************************
************ Transistor: Mn15x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.739823 stddev: 0.0137728
*************************************************************
************ Transistor: Mn10x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: 0.737496 stddev: 0.0132078
*************************************************************
************ Transistor: Mn5x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.743991 stddev: 0.0174955
*************************************************************
************ Transistor: Mn15x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure :
72
Short on Gate : 4
***** Threshold Voltage:
VBS: 0 NoTrn: 72 mean: 0.736225 stddev: 0.0132082
*************************************************************
************ Transistor: Mn5x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: 0.74334 stddev: 0.0168014
*************************************************************
************ Transistor: Mn10x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.735377 stddev: 0.0123188
*************************************************************
************ Transistor: Mn15x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure : 74
Short on Gate : 1
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.733071 stddev: 0.0106708
============ cmos58-6 =============
******************************************************
***Sheet Resistance Summary************
Name: scbrp+, Mean: 166.939, Std Dev: 4.14454
Name: scbrn+, Mean: 327.579, Std Dev: 104.075
Name: scbrPO, Mean: 31.9515, Std Dev: 0.853549
******************************************************
***Contact Resistance Summary************
Name: conrp+, Mean: 39.2092, Std Dev: 0.5969
Name: conrn+, Mean: 34.356, Std Dev: 1.69499
Name: conrpo, Mean: NaN, Std Dev: NaN
*************************************************************
************ Transistor: Mp10x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:10
No catastrophic failure :
66
Short on Gate : 3
Short on Body : 1
Open on Gate : 2
Open on Body : 4
***** Threshold Voltage:
VBS: 0 NoTrn: 66 mean: -0.734301 stddev: 0.0576278
*************************************************************
************ Transistor: Mp5x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:23
No catastrophic failure :
53
Short on Gate : 1
Open on Gate : 1
Open on Body :
21
***** Threshold Voltage:
VBS: 0 NoTrn: 53 mean: -0.691821 stddev: 0.0831888
*************************************************************
************ Transistor: Mp15x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:6
No catastrophic failure :
70
Short on Gate : 4
Short on Body : 1
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 35 mean: -0.784656 stddev: 0.0399739
*************************************************************
************ Transistor: Mp10x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure :
72
Short on Gate : 1
Short on Body : 1
Open on Gate : 1
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 72 mean: -0.826394 stddev: 0.026533
*************************************************************
************ Transistor: Mp5x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure :
72
Open on Gate : 1
Open on Body : 3
***** Threshold Voltage:
VBS: 0 NoTrn: 72 mean: -0.800376 stddev: 0.0631959
*************************************************************
************ Transistor: Mp15x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure :
72
Short on Gate : 1
Short on Body : 2
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 71 mean: -0.839456 stddev: 0.0171577
*************************************************************
************ Transistor: Mp5x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.881291 stddev: 0.0360816
*************************************************************
************ Transistor: Mp10x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure :
73
Short on Gate : 2
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: -0.869459 stddev: 0.0172557
*************************************************************
************ Transistor: Mp15x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure :
73
Short on Gate : 1
Short on Body : 1
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: -0.868755 stddev: 0.0119626
*************************************************************
************ Transistor: Mp5x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.913186 stddev: 0.0231207
*************************************************************
************ Transistor: Mp10x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure :
72
Short on Gate : 2
Short on Body : 1
Short between Drain & Source :
1
***** Threshold Voltage:
VBS: 0 NoTrn: 72 mean: -0.892794 stddev: 0.0156336
*************************************************************
************ Transistor: Mp15x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure :
73
Short on Gate : 1
Short on Body : 1
Open on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: -0.890567 stddev: 0.012064
*************************************************************
************ Transistor: Mp5x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure : 76
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.933903 stddev: 0.0200419
*************************************************************
************ Transistor: Mp10x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 1
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: -0.904699 stddev: 0.0170346
*************************************************************
************ Transistor: Mp15x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: -0.898881 stddev: 0.012504
*************************************************************
************ Transistor: Mp10x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.937659 stddev: 0.0141347
*************************************************************
************ Transistor: Mp5x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: -0.977176 stddev: 0.029397
*************************************************************
************ Transistor: Mp15x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure : 76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.928501 stddev: 0.0123609
*************************************************************
************ Transistor: Mp10x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 70 mean: -0.942546 stddev: 0.0138407
*************************************************************
************ Transistor: Mp5x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.974302 stddev: 0.0314803
*************************************************************
************ Transistor: Mp15x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.931534 stddev: 0.0108675
*************************************************************
************ Transistor: Mp5x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.963258 stddev: 0.0285593
*************************************************************
************ Transistor: Mp10x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: -0.937393 stddev: 0.0113617
*************************************************************
************ Transistor: Mp15x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 63 mean: -0.927701 stddev: 0.00861763
*************************************************************
************ Transistor: Mn10x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:16
No catastrophic failure :
60
Short on Gate :
14
Open on Source or Drain : 1
Open on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 60 mean: 0.722413 stddev: 0.0274935
*************************************************************
************ Transistor: Mn5x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:5
No catastrophic failure :
71
Short on Gate : 4
Open on Source or Drain : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 71 mean: 0.703339 stddev: 0.0477258
*************************************************************
************ Transistor: Mn15x0.8
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:15
No catastrophic failure :
61
Short on Gate :
14
Open on Source or Drain : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 61 mean: 0.723185 stddev: 0.0245621
*************************************************************
************ Transistor: Mn10x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:11
No catastrophic failure :
65
Short on Gate :
10
Short on Body : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 65 mean: 0.737052 stddev: 0.0239133
*************************************************************
************ Transistor: Mn5x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.727786 stddev: 0.0389144
*************************************************************
************ Transistor: Mn15x0.9
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:7
No catastrophic failure :
69
Short on Gate : 7
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: 0.732711 stddev: 0.0214373
*************************************************************
************ Transistor: Mn5x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:3
No catastrophic failure : 73
Short on Gate : 3
***** Threshold Voltage:
VBS: 0 NoTrn: 73 mean: 0.737294 stddev: 0.0342416
*************************************************************
************ Transistor: Mn10x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:9
No catastrophic failure :
67
Short on Gate : 9
***** Threshold Voltage:
VBS: 0 NoTrn: 67 mean: 0.741252 stddev: 0.0203657
*************************************************************
************ Transistor: Mn15x1.0
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:11
No catastrophic failure :
65
Short on Gate : 6
Short on Body : 5
***** Threshold Voltage:
VBS: 0 NoTrn: 65 mean: 0.735492 stddev: 0.0206078
*************************************************************
************ Transistor: Mn5x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.741476 stddev: 0.0314351
*************************************************************
************ Transistor: Mn10x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:8
No catastrophic failure :
68
Short on Gate : 8
***** Threshold Voltage:
VBS: 0 NoTrn: 68 mean: 0.7418 stddev: 0.0190517
*************************************************************
************ Transistor: Mn15x1.1
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:6
No catastrophic failure :
70
Short on Gate : 6
***** Threshold Voltage:
VBS: 0 NoTrn: 70 mean: 0.735377 stddev: 0.0196779
*************************************************************
************ Transistor: Mn5x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.742027 stddev: 0.0296909
*************************************************************
************ Transistor: Mn10x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:7
No catastrophic failure :
69
Short on Gate : 7
***** Threshold Voltage:
VBS: 0 NoTrn: 69 mean: 0.742842 stddev: 0.0179007
*************************************************************
************ Transistor: Mn15x1.2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:4
No catastrophic failure : 72
Short on Gate : 4
***** Threshold Voltage:
VBS: 0 NoTrn: 72 mean: 0.734579 stddev: 0.0190452
*************************************************************
************ Transistor: Mn10x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.737541 stddev: 0.0147493
*************************************************************
************ Transistor: Mn5x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.743236 stddev: 0.0238761
*************************************************************
************ Transistor: Mn15x2
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:2
No catastrophic failure :
74
Short on Gate : 2
***** Threshold Voltage:
VBS: 0 NoTrn: 74 mean: 0.731595 stddev: 0.0151564
*************************************************************
************ Transistor: Mn10x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.733928 stddev: 0.0129536
*************************************************************
************ Transistor: Mn5x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure : 76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.741306 stddev: 0.0218808
*************************************************************
************ Transistor: Mn15x3
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: 0.726299 stddev: 0.0159693
*************************************************************
************ Transistor: Mn5x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.74039 stddev: 0.0193612
*************************************************************
************ Transistor: Mn10x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:1
No catastrophic failure :
75
Short on Gate : 1
***** Threshold Voltage:
VBS: 0 NoTrn: 75 mean: 0.73092 stddev: 0.0107697
*************************************************************
************ Transistor: Mn15x5
***** Catastrophic Failure Test:
Transistors Tested: 76, Failed:0
No catastrophic failure :
76
***** Threshold Voltage:
VBS: 0 NoTrn: 76 mean: 0.726413 stddev: 0.00950432
=============================================================================
Process Log: cmos58
Modified: Mon May
1 12:56:43 PDT 2000
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Operator:
Date:
Step Number:
Step Title:
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Procedure:
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