Run cards of the CMOS Baseline 200 process

Step 0. Starting wafers

Step 1. Initial oxidation

Step 2. Zero layer photo

Step 3. Scribe wafers

Step 4. Zero layer etch

Step 5. Pad oxidation Nitride deposition

Step 6. N-well photo

Step 7. Nitride etch

Step 8. N-Well implant

Step 9. Nitride Removal

Step 10. Pad oxidation Nitride deposition

Step 11. P-Well Photo

Step 12. Nitride etch

Step 13. P-Well implant

Step 14. Nitride removal

Step 15. Well drive-in

Step 16. Pad oxidation/nitride deposition

Step 17. Active area photo

Step 18. Nitride etch

Step 19. P-Well field implant photo

Step 20. P_Well field implant

Step 21. LOCOS oxidation

Step 22. Nitride removal

Step 23. Sacrificial oxidation

Step 24. Screen oxidation

Step 25. NMOS Vt implant photo

Step 26. NMOS Vt implant

Step 27. PMOS Vt implant photo

Step 28. PMOS Vt implant

Step 29. Gate oxidation /Poly deposition

Step 30. Poly gate photo

Step 31. Poly-Si etch

Step 32. PMOS LDD implant photo

Step 33. PMOS LDD implant

Step 34. NMOS LDD implant photo

Step 35. NMOS LDD implant

Step 36. LDD spacer deposition

Step 37. LDD spacer formation

Step 38. P+ gate & S/D photo

Step 39. P+ gate & S/D implant

Step 40. N+ gate & S/D photo

Step 41. N+ gate & S/D implant

Step 42. Back side etch

Step 43. Gate & S/D annealing

Step 44. Silicidation

Step 45. PSG Deposition and Densification

Step 47. Contact photo and etch

Step 48. Metal1 deposition

Step 49. Metal1 photo

Step 50. Metal1 etch

Step 51. Sintering

Step 52. Testing

Step 53. Dielectric deposition & planarization

Step 54. Via1 photo

Step 55. Via1 etch

Step 56. Metal2 deposition

Step 57. Metal2 photo

Step 58. Metal2 etch

Step 59. Testing