CMOS Baseline at UC Berkeley Microlab
General Baseline Information
Introduction
Microlab Memoranda
Microlab Contacts
Baseline Engineers
Baseline Reports
Report VIII: 0.35 um CMOS Process on Six-Inch Wafers The First Baseline Run in the New Marvell Nanolab by A. Szucs
Report VII: 0.35 um CMOS Process on Six-Inch Wafers by L. Petho
Report VI: 0.35 um CMOS Process on Six-Inch Wafers by L. Petho & A. Pongracz
Report V: 0.35 um CMOS Process on Six-Inch Wafers by A. Pongracz & G. Vida
Report IV: 0.35 um CMOS Process on Six-Inch Wafers (pdf) by A. Horvath, S. Parsa, H.Y. Wong
Report III: Six-Inch CMOS Baseline Process (pdf) by L. Voros, S. Parsa
Report II: CMOS Baseline Process (pdf) by L. Voros
Report I: CMOS Baseline Process (pdf) by S. Fang
Members Only
CMOS 200 Process Log
CMOS 190 Process Log
CMOS 180 Process Log
CMOS 170 Process Log
Four-Inch Runs
CMOS 61
:
NVt,
PVt,
Resistivity
CMOS 60
:
NVt,
PVt,
Resistivity
CMOS 59
:
NVt,
PVt,
Resistivity
CMOS 58
:
NVt,
PVt,
Resistivity
Six-Inch Runs
CMOS 190 (0.35 um)
CMOS 180 (0.35 um with Mix&Match and STI)
CMOS 170 (advanced 0.35 um)
CMOS 161 (0.35 um)
CMOS 150 (1.3 um)
Graphics
Baseline Process Cross-section (pdf)
