FlexFET NMOS/CMOS Process Flow Details                  
Contact info:  Dr. Stephen Parke, sparke@boisestate.edu (208) 426-3842 or 465-7712 or Mike Goldston, mikegoldston@americansemi.com (208) 336-2773, or Doug Hackler, doughackler@americansemi.com (208) 336-2773                  
American Semiconductor will provide a GDS file of our 8.5 x 8.5mm test chip with 8 mask layers                  
Run NMOS and CMOS short-loop wafers on 150mm SOI substrates supplied by ASI, plus bulk control wafers.                  
NMOS shortloop uses only 6 masks and masking steps.  The CMOS shortloop uses 8 masks and 10 masking steps (the NMOS/PMOS masks are used twice). These counts do NOT include Zero level alignment marks.                  
                           
  Combined Flow MASK SEQUENCE: Matching Process Sequential Step No. Wafer No's masked Berkeley Reticle Name                  
  ZERO 5 All UCB Combi                  
  NMOS 9 1,3,7,8 FlexFET2                  
  PMOS 12 1,3,7,8 FlexFET2                  
  ACTIVE AREA 18a, 18b All FlexFET1                  
  PMOS 25 1,3,5,6,7,8,9,10 FlexFET2                  
  NMOS 33 1,3,5,6,7,8,9,10 FlexFET2                  
  BOTTOM GATE 39 All FlexFET1                  
  TOP GATE 48 All FlexFET1                  
  GATE CONTACT 52 All FlexFET2                  
  S/D CONTACT 60 All FlexFET1                  
  METAL 1 65 All FlexFET2                  
                           
               
Seq. Step No. COMBINED NMOS/CMOS PROCESS SEQUENCE TOOL / RECIPE TARGET SPEC Notes SPLIT INFORMATION     (Split points highlighted in Yellow; Photo steps highlighted in Green) Completion Date              
1 STARTING WAFERS SIMGUI Low-Dose SIMOX <100> FZ, 1200-2300 ohm-cm, 1E13 Boron SIMOX SOI                                        Silicon layer= 0.187um     BOX=0.15 um 15 150mm SOI wafers + Bulk controls   10/23/2003              
2 SCRIBE WAFERS Manual Scribe SOI Wafers #01 to #15     10/23/2003              
SPLIT POINT#1: Thin vs. Thick SOI       Split #1: Thin vs. Thick SOI                
3 Grow thick sac oxide on thin SOI split Tystar2, @WETOXA; Thermal Oxidation 1000˚C, 10 min; Target = 1000 A  Measured thickness: 1014 - 1067 A Thinned SOI only           wa# 1, 3,4,5,6,11,12 10/23/2003              
4 Wet strip sac oxide Sink6, 25:1 HF; 9 min Strip thermal oxide   Thinned SOI only           wa# 1, 3,4,5,6,11,12 10/27/2003              
5 ZERO LAYER PHOTO ASML DUV Std. Litho w/ BARC; Combi Reticle Exposure: 45 mJ/cm2 All Wafers 11/24/2003              
6 ZERO LAYER ETCH Lam4 Etch 1200A - 1900 A Si Etch through SOI. Stop on BOX All Wafers (wafer #4 scrapped) 11/26/2003              
7 RESIST STRIP & CLEAN Matrix + Technics-C Matrix O2 Ash + Technics-C O2 Ash + Std. MEMS Piranha Clean in Sink8 Alignment Mart Trench Depth Measured After Strip All Wafers 11/26/2003 to 12/01/2003              
SPLIT POINT #2: Implanted S/D vs. Silicide S/D       Split #2, Implanted  S/D vs. Silicide                
8 SCREEN OXIDATION Tystar2, 2DRYOXA Thermal OX, 900 ˚C, Target = 100 A 98 A - 101 A Implanted S/D wafers only: wa# 1,3,7,8,11,13,14 12/2/2003              
9 NMOS PHOTO ASML DUV Std. Litho w/ BARC; FlexFET2 Reticle Exposure: 45 mJ CMOS Implanted S/D wafers only: wa# 1,3,7,8 12/3/2003 to 12/05/2003              
10 N+ SD IMPLANT CORE Systems Energy/Dose:  AS, 1E15, 40keV, 7 deg Implanted at Core Systems Implanted S/D wafers only: wa# 1,3,7,8,11,13,14 12/05/2004 to 12/9/2003              
11 RESIST STRIP & CLEAN Matrix O2 Ash, 1.5 min + Std. Clean, Sink8; NO HF     CMOS Implanted S/D wafers only: wa# 1,3,7,8 12/10/2003              
12 PMOS PHOTO ASML DUV Std. Litho w/ BARC; FlexFET2 Reticle Exposure: 40 mJ CMOS Implanted S/D wafers only: wa# 1,3,7,8 12/10/2003 to 12/11/2003              
13 P+ SD IMPLANT CORE Systems Energy/Dose: BF2, 2E15, 20 keV, 7 deg Implanted at Core Systems CMOS Implanted S/D wafers only: wa# 1,3,7,8 12/11/2004 to 12/14/2003              
14 RESIST STRIP & CLEAN NO HF Matrix O2 Ash, 1.5 min+ Std. Clean, Sink8, no HF dip   CMOS Implanted S/D wafers only: wa# 1,3,7,8 12/15/2003              
15 SPUTTER TITANIUM Novellus Temp. 300 ˚C; Pre-heat, 60 sec; Power 900 W; Dep Tim, 33 sec Target 400 A Silicide wafers only: wa# 2,5,6,9,10,12,15 12/16/2003              
16 IMPLANTED S/D Activation RTA: Heatpulse3 450 ˚C, 30 sec + 1000 ˚C, 10 sec, N2   Implanted S/D wafers only: wa# 1,3,7,8,11,13,14 12/16/2003 to 12/17/2003              
17a NITRIDE PAD DEPOSIT (Implanted S/D) TYSTAR9, 9SNITA 43 min; 800 ˚C: 1500A target Measured thickness: 1730 A - 1876 A Implanted S/D wafers only: wa# 1,3,7,8,11,13,14 12/18/2003              
17b NITRIDE PAD DEPOSIT (Silicide S/D) PQECR (PECVD) Room Temp; 30 mTorr, 265 sec dep time: 1500A   Silicide wafers only: wa# 2,5,6,9,10,12,15 (wa#15 scrapped) 02/20/2004 to 02/23/2004              
18a ACTIVE AREA PHOTO (Implanted S/D) ASML DUV Std. Litho w/ BARC; FlexFET1 Reticle Exposure: 44 mJ Wafers 1,3,7,8,11,13,14 12/18/2004              
18b ACTIVE AREA PHOTO (Silicide S/D) ASML DUV Std. Litho w/ BARC; FlexFET1 Reticle Exposure: 110 mJ Silicide wafers only: wa# 2,5,6,9,10,12,15 3/1/2004              
19a NITRIDE PAD ETCH (Implanted S/D) Lam4 + Applied Centura MPX Chamber Anisotropic Etch 1500A Nitride Pad   Leave resist Implanted S/D wafers only: wa# 1,3,7,8,11,13,14 (wafer #8 scrapped) 12/192003 to 02/04/2004              
19b NITRIDE PAD ETCH (Silicide S/D) Applied Centura, MPX Chamber Anisotropic Etch 1500A Nitride Pad   Leave resist Silicide wafers only: wa# 2,5,6,9,10,12,15 3/4/2004              
20a SILICON ETCH (Implanted S/D) Applied Centura, DPS Chamber, Recipe DPS_SI_ETCH Anisotropic Etch 1100 and 1300 A   Implanted S/D wafers only: wa# 1,3,4,7,8,11,13,14 (wafer #1 scrapped) 3/12/2004              
20b Ti  ETCH (Silicide S/D) Wet Etch, Sink7, H2SO4, 95˚C  400 A (See RunCards for Detailsand Etch Times) Stop on Silicon Silicide wafers only: wa# 2,5,6,9,10,12,15 4/05/2004 to 4/14/2004              
21 RTA SILICIDE REACTION Heat Pulse3, 600˚C, 60 sec, Argon RTA silicidation   Silicide wafers only: wa# 2,5,6,9,10,12,15 4/15/2004              
22a RESIST STRIP & CLEAN (Implanted S/D) Resist removed after Si Etch (Step 20a): Matrix O2 Ash (2.5 min) + NON-MOS Pirhana Sink8  (10 min) + MOS Pirhana, Sink8 (10 min) + 10:1 HF dip (10 sec)   Implanted S/D wafers only: wa# 1,3,4,7,8,11,13,14 3/12/2004              
22b RESIST STRIP & CLEAN (Silicide S/D) Resist removed prior to Ti Etch (Step 20b): PRS-3000, 10 hours     Implanted S/D wafers only: wa# 1,3,4,7,8,11,13,14 4/2/2004              
23 PSG SPACER DEPOSITION Applied P5000 PSG (1%-5%); dep time 19 sec PSG thickness: 1500 A All remaining wafers 4/19/2004              
24 PSG SPACER ETCH Applied Centura, MXP_OXSP_ETCH Recipe MXP_OXSP_ETCH with auto endpoint detect Etch times 25 sec and 27 sec All remaining wafers: wa# 2,3,5,6,7,9,10,11,12,13,14 (wafer #11 sacrificed for SEM X-section analysis) 4/20/2004              
25 PMOS PHOTO ASML DUV (no BARC) Dark Field, FlexFET2 Reticle  Exposure: 80mJ for CMOS silicide wafers; 145 mJ for CMOS S/D wafers Remaining CMOS wafers only:wa# 3,5,6,7,9,10 4/23/2004              
SPLIT POINT #3: BOTG and THRESHOLD IMPLANTS       Split #3, Shallow vs. Deep Bot Gate and Vt Adjust Implants                
26 PMOS-BOTTOM GATE / Vt ADJUST IMPLANTS Phosphorous, Antimony and BF2 Implants (see Split Table) Split Table Attached Implanted at Core Systems CMOS wafers: wa# 3,5,6,7,9,10.  See Split Table 04/28/2004 to 05/05/2004              
27 Wet ETCH PSG Sink8 Wet Etch Remove N+ doped spacer material from PMOS regions CMOS wafers only:wa# 3,5,6,7,8,9,10 5/5/2004              
28 RESIST STRIP & CLEAN Matrix Asher + Sink5 and Sink8 O2 Ash 2 min Sink5, PRS-3000, Silicide wafers;Sink8, Piranha, Implant S/D wafers CMOS wafers only:wa# 3,5,6,7,8,9,10 5/5/2004              
29 RTA DRIVE Heatpulse3 RTA, 950 C, 10 sec   CMOS wafers only:wa# 3,5,6,7,8,9,10 5/5/2004              
30 STRIP PSG Sink8 Wet Etch, 5:1 BHF Silicide, 14 sec; Implanted S/D, 20 sec CMOS wafers only:wa# 3,5,6,7,8,9,10 5/5/2004              
31 BSG SPACER DEPOSITION  Applied P5000 18 sec dep time, 1500 A target Wa#7=1540A; wa#3=1560A CMOS wafers only:wa# 3,5,6,7,8,9,10 5/6/2004              
32 BSG SPACER ETCH Applied Centura, MXP_OXSP_ETCH Endpointed: etch times 31-33 sec   CMOS wafers only:wa# 3,5,6,7,8,9,10 5/7/2004              
33 NMOS PHOTO ASML DUV Dark Field; FlexFET2 Reticle Opens NMOS areas for BSG removal CMOS wafers only:wa# 3,5,6,7,8,9,10 05/07/2004 to 05/10/2004              
34 NMOS-BOTTOM GATE / Vt ADJUST IMPLANTS Boron, Indium, Arsenic Implants (see Split Table)  Split Table Attached Implanted at Core Systems All remaining wafers: #2,3,5,6,7,9,10,12,13,14.  See Split Table 5/10/2004 to 5/13/2004              
35 Wet ETCH BSG Sink8 and Sink9 Wet Etch: Sink8, 5:1 BHF, Implanted S/D wafers; Sink9,10:1 BHF, Silicide wafers Remove P+ spacer material from NMOS regions CMOS wafers only:wa# 3,5,6,7,8,9,10 5/18/2004              
36 RESIST STRIP & CLEAN Matrix Asher + Sink5 and Sink8 O2 Ash, 2 min Sink5, PRS-3000, Silicide wafers;Sink8, Piranha, Implant S/D wafers CMOS wafers only:wa# 3,5,6,7,8,9,10 5/19/2004              
37 RTA DRIVE Heatpulse3 RTA, 1000 C, 10 sec   All remaining wafers: #2,3,5,6,7,9,10,12,13,14.  See Split Table 5/20/2004              
38 STRIP BSG   Wet Etch Remove BSG from CMOS wafers; Remove PSG from NMOS wafers. All remaining wafers: #2,3,5,6,7,9,10,12,13,14.  See Split Table 5/20/2004              
39 BOTTOM GATE PHOTO ASML DUV Light Field; FlexFET1 Reticle Protects channel regions.  New ASML alignment marks created. All remaining wafers 5/27/2004              
40 SILICON ETCH Centura DPS, DPS_SI_ETCH Selectivity:  Si:PQECR Nitride, ~12:1; Si:LPCVD Nitride, ~5:1 Etch down to BOX everywhere except channel regions All remaining wafers 5/28/2004              
41 RESIST STRIP & CLEAN       All remaining wafers 6/1/2004              
42 SACRIFICIAL OXIDATION Thermal Oxide Target: 100 A, 850˚C , 60 min, dry O2, no anneal Measured Tx=81 A (Sopra ellipsometer) All remaining wafers 6/4/2004              
43 NITRIDE SPACER DEPOSITION Oxford Plasmalab 100 PECVD Target Tx = 1100 A; Measured Tx= 1030 A, RI=1.96 Nitride Spacer Film Deposited at WTC All remaining wafers 6/4/2004 to 6/9/2004              
44 NITRIDE SPACER ETCH Applied Centura MXP_NITSP_ETCH Etch 900 A Si3N4 to form sidewall spacers Etch manually endpointed, etch times 18-20 sec All remaining wafers 6/11/2004              
45 SAC OXIDE STRIP & CLEAN Wet dip 25:1 HF Silicide wafers, 35 sec; Implanted wafers, 60 sec   All remaining wafers 6/13/2004              
46 GATE OXIDATION Tystar1, TCA clean overnight, 1FLXGATE Target 50 A, 900˚C, 4 min O2 + 16 min N2 anneal Oxide Tx = 51 A on test wafer All remaining wafers 6/14/2004              
SPIT POINT #4: Ti GATE vs. POLY GATE       Split #4, Titanium vs. N+ Poly Gate                
47a N+ POLY TOPGATE DEPOSITION Tystar10, 10SDPLYA Poly dep, 25 in, target 500 A Phos doped polysilicon Poly Gate Wafers: wa# 5,7,9,12,13 6/15/2004              
47b TiN/POLY TOPGATE  DEPOSITION Novellus, TiN600ST; Tystar16, 16SDPLYB Ti Nitride, 600 A + 600 A Poly silicon, see Split Table Poly deposition on TiN wafers requred due to step coverage cioncerns with TiN TiN Gate Wafers: wa# 2,3,6,10,14 6/15/2004 to 6/19/2004              
48 TOPGATE PHOTO ASML DUV (without BARC) Light Field; FlexFET1 Reticle Expose Poly group: 21 mJ @ 0.5 um focus offset; TiN+Poly group: 20 mJ @ 0.8 um offset All remaining wafers 6/21/2004              
49a TOPGATE ETCH (POLY Gate) Applied Centura DPS, DPS_SI_ETCH Plasma Etch Poly Gate, 12 sec + O2 Ash, 7 min. + 100:1 H2O:HF dip, 1 min. See Run Cards for more data. Channel Si Etch to be done at Gate Contact Etch Poly Gate Wafers: wa# 5,7,9,12,13 06/21/2004 to 6/24/2004              
49b TOPGATE ETCH (TiN Gate + Poly Cap) Applied Centura DPS (DPS_SI_ETCH) + Wet Etch Plasma Etch Poly Cap +Wet Etch TiN TopGate (1:1 NH4OH: H2O2 + 30 sec 25:1 HF:H2O) See Run Cards for more data. Channel Si Etch to be done at Gate Contace Etch TiN Gate Wafers: wa# 2,3,6,10,14 06/21/2004 to 06/29/2004              
50 RESIST STRIP & CLEAN Poly Gate: Ash +100:1 HF; TiN Gate: Ash + 30 sec Piranha      All remaining wafers 6/29/2004              
51 STI TEOS DEPOSITION P5000, TEOS Dep + Etchback 1st cylce: 110 sec TEOS dep + 120 sec etchback; 2nd cycle 90 sec dep + 120 sec etchback Total TEOS thickness on test wafers, 8507 A - 9015 A All remaining wafers 7/9/2004              
52 STI OXIDE PLANARIZATION Resist Etchback in Applied Centura MXP (Note: Decision made to eliminate oxide CMP step; CMP tool down) DUV-210; resist Tx = 11000 A; Etchback with MXP_PREETCHBACK recipe TEOS remaining Tx = 5949 A - 7645 A All remaining wafers 7/9/2004              
53 GATE CONTACT (M0) PHOTO ASML DUV Dark Field; FlexFET2 Reticle Defines contacts to bottom and top gates; forms damascene M0 interconnect All remaining wafers 7/9/2004              
54 GATE CONTACT (M0) and CHANNEL ETCH Centura MXP MXP_OXSP_ETCH + MXP_NITRSP_ETCH Etch Gate Contacts to TopG and BotG + Channel Si Overetch All remaining wafers 7/14/2004              
55 RESIST STRIP Matrix Ash, 2min + Pirahna clean, 1 min     All remaining wafers 7/15/2004              
56 METAL 0 DEPOSITION Novellus + Tystar10 Sputter Etch clean + Deposit 600 A TiN + 7000 A Polysilicon   All remaining wafers 7/15/2004 to 7/22/2004              
57 M0 POLY/TiN CMP IPEC/Westec 472 Avanti 4.5 sec poly polish + 45 sec oxide polish Must clear TiN/poly from cross-bars All remaining wafers 0730/204              
58 POST CMP CLEAN Wet Dip, Sink7 100:1 HF, 1 min   All remaining wafers 8/3/2004              
59 ILD OXIDE DEPOSITION Applied P5000, Recipe AH_USG  25 sec, 80 A/sec Target 2000 A; Range 2051 A to 2102 A All remaining wafers 8/3/2004              
60 S/D CONTACT PHOTO ASML DUV, w/o BARC Dark Field reticle; S/D Imp wafers: exp 45 mJ, 1.1 um focus offset; silicide wafers: 47 mJ, 1.1 um offset Defines contacts to S/D (wa#2 misaligned, opend PM die and etch top layer); hard bake 120 C, 1 hr All remaining wafers 8/4/2004              
61 S/D CONTACT ETCH Centura MXP, MXP_OXSP_ETCH + MXP_NIT_ME Etch ILD + Nitride pad; see run cards for details Form S/D contacts All remaining wafers 8/5/2004              
62 RESIST STRIP Matrix, O2 Ash, 1.5 min     All remaining wafers 8/9/2004              
63 ALUMINUM M1 DEPOSITION Novellus/Sink6 +CPA sputter deposition Silicide wafers: Sputter etch , ETCH_STD, 1 min; Implanted wafers: 25:1 HF, 30 sec Al Dep: 6 mT, 4 kW, 80 cm/min (~850A/pass); silicided wa: ~5200A; imp wa: ~6000A All remaining wafers 8/10/2004              
64 M1 PHOTO ASML DUV, with BARC Light Field Reticle; exp = 32 mJ at 1.1 um focus offset Hard bake: UVBAKE, program J All remaining wafers 8/10/2004              
65 M1 ALUMINUM ETCH BARC etch in Centura MXP + Al etch in Lam3  MXPBARC_ETCH, 40 sec +Al Std. Al plama etch Silicide wafers: 65 sec; Implanted wafers: 75 sec All remaining wafers 8/11/2004              
66 RESIST STRIP Matrix O2 Ash, 1.5 min + DI rinse +SRD     All remaining wafers 8/11/2004              
67 ANNEAL (SINTER) Forming gas 400C 20min     All remaining wafers 8/11/2004              
68 FINAL TESTING       All remaining wafers