Step 41. Gate & S/D annealing

Step	Process	Date	Operator
41.1	Remove PR in O2 plasma in Matrix.	11/16/04	Horvath
41.2	Standard clean wafers in sink8 (MEMS) and sink6 (MOS) piranha. No dip. Include all monitor wafers.
41.3	RTA annealing in Heatpulse3. Device chamber. Recipe: 1050RTA6.RCP 450C 30 sec 900C 10 sec 1050C 5 sec
41.4	Check Rs using 4 point probe on monitor wafers: NCH: 40 Ohm/sq PCH: 80 Ohm/sq Tpoly1 (P+): 200 Ohm/sq