Step 34. LDD spacer deposition

 

 

 

 

Step

 

Process

Date

Operator

 

34.1

 

 

- Remove PR in O2 plasma (Matrix)
- Std. clean wafers in sink8 (MEMS) and sink6 (MOS) piranha

Include 3 dummies for oxide etch test

 

11/04/04
-
11/05/04

Horvath

 

34.2

 
TEOS deposition in P-5000:

- Dep. rate is 80A/min, target thikness is 4000A.
- Dep. time: 50 sec


Note1: Targeted spacer thikness is ~3000A. Tests show: spacer thikness = deposited TEOS x ~0.6

Note2: Particles deposited on the left side of each wafer in a half inch wide line. That area will not likely yield.

TEOS thickness:


 T
 C
 F
 L
 R
w#7
 3595
 4144
 4203
 4166
 4143
w#4
 4007
 4119
 4236
 4149
 4114


 

34.3

 

 

Annealing in Tystar2:

Recipe 2HIN2ANA, 900C, 30 min.

Note: Anneal for TEOS would not be necessary, but performed because the simulation also included.

 

 

34.4

 

 

TEOS thickness after annealing:


 T
 C
 F
 L
 R
w#7
 3848
 3871
 4056
 3987
 3969
w#4
 3879
 3896
 4073
 4032
 3984


Note: The difference in thickness results between before and after annealing can be due to reflective index change (not necessary thickness change)