Microlab CMOS Process

Version 8.1 (2005)

0.35 um, twin-well, 150 mm, double poly-Si, metal

(6" process)

 

CMOS run for n-channel and p-channel transistor fabrication with advanced process

modules such as LDD and silicide. Mask set is basically the same what was used

for the first 6-inch baseline process (CMOS150) except the S/D and contact masks.

It enables to print 0.4 micron device, the S/D masks were modified to implant the entire poly area.

 

    ________________________________________________________________________

            0.0 Starting Wafers (10):  36-63 ohm-cm, p-type, <100>, 6"

    ________________________________________________________________________

            1.0 Initial Oxidation:  target = 25 (+/- 5%) nm

                        Include 2 dummies for PM etch characterization.

    ________________________________________________________________________

1.1 TLC clean furnace tube (tystar2)

    _______________________________________________________________________

1.2 Standard clean wafers in sink9 (MOS side):

10/1 HF dip until dewet, spin-dry.

    ________________________________________________________________________

1.3 Dry oxidation at 950 C (2DRYOX):

30 min. dry O2

20 min. dry N2

Measure oxide thickness Tox=

    ________________________________________________________________________

2.0 Zero Layer Photo

Standard DUV lithography process:

HMDS (program 1 on svgcoat6), coat (program 2 on svgcoat6),

RPM=1480, UV210-0.6), soft bake (130 C proximity),

Expose (ASML, zero marks mask, 30 mJ/cm2),

PEB (program 1, 130 C on svgdev6) ,

Develop (program 1 on svgdev6).

Hard bake: UVBAKE (program J)

   ________________________________________________________________________

 

 

2.1 Etch zero layer into the substrate:

                        a) Etch oxide in lam2 SIO2MON recipe.

                        Check actual etch rate, adjust time.

                        b) Etch silicon in lam4

                        (target depth=1200 A,) recipe=6000, etch time 30 sec.

Note: Other option lam4 recipe 6200, SF6=25 sec, Cl2=30 sec

(recipe 200 and 6000 merged together)

c) Scribe lot and wafer number on each wafer, including controls.

                                    Ash photoresist in matrix.

                                    d) Measure the depth of the alignment marks using asiq.

    ________________________________________________________________________

3.0 Pad Oxidation/Nitride Deposition:

target = 25 nm SiO2 + 180 nm Si3N4

    ________________________________________________________________________

3.1 TLC clean furnace tube (tystar2).  Reserve tystar9.

    ________________________________________________________________________

3.2 Standard clean wafers in sink9

(MEMS and MOS, dip into HF 25:1 until dewet).

                      Include NCH, PCH control wafers.

    ________________________________________________________________________

3.3 Dry oxidation at 1000 C (2DRYOX):

21 min. dry O2

15 minutes dry N2 anneal.

Measure the oxide thickness on PCH and NCH.

    ________________________________________________________________________

3.4 Deposit 180 nm of Si3N4 immediately (9SNITA):

approx. time = 55 min., temp.= 800 C.

Measure nitride thickness. (nanospec).

    ________________________________________________________________________

4.0 N-Well Photo:

                                    Standard DUV lithography process.

Mask: N-well (dark field)

                                    Standard oven bake (30 min., 120 C)

    _______________________________________________________________________

 

 

    ________________________________________________________________________

5.0 Nitride Etch:

Plasma etch nitride in lam4.    Recipe: 200

Power:125 W         Time:~85 sec.        Overetch: no

Selectivity: Si3N4:PR=1:1

Measure Tox on each work wafer. (2 pnts measurement).

Do not remove PR. Inspect.

Measure PR thickness covering active area.tpr >= 700nm

Hard bake again ( 2 hours, 120 C)

    ________________________________________________________________________

6.0 N-Well Implant: Include PCH.

split: wafers #1-5, PCH: phosphorus, 1E13/cm2, 150 KeV.

                                            wafers #6-10: phosphorus, 2E13/cm2, 150 KeV.

    ________________________________________________________________________

7.0 Nitride removal:

    _______________________________________________________________________

                        7.1. Remove PR in Matrix. Clean wafers in sink9 MEMS piranha

    _______________________________________________________________________

7.2. Etch nitride in fresh 160 C phosphoric acid in sink7 (~4 hours)

    ________________________________________________________________________

                        7.3. Etch pad oxide in 5:1 BHF at sink7 until dewet. Include NCH, PCH.

    ________________________________________________________________________

            8.0 Pad Oxidation/Nitride Deposition:

Target = 25 nm SiO2 + 180 nm Si3N4

    ________________________________________________________________________

8.1 TLC clean furnace tube (tystar2).  Reserve tystar9.

    _______________________________________________________________________

8.2 Standard clean wafers in sink9 (MEMS, MOS, 25:1 HF dip

until dewet). Include NCH, PCH.

    ________________________________________________________________________

8.3 Dry oxidation at 1000 C (2DRYOXA):

21 min. dry O2

15 minutes dry N2 anneal.

Measure the oxide thickness on NCH and PCH.

    ________________________________________________________________________

8.4 Deposit 180 nm of Si3N4 immediately (9SNITA):

Approx. time = 55 min., temp = 800 C.

    ________________________________________________________________________

9.0 P-Well Photo:

                                    Standard DUV lithography process. Mask: PWELL (inverse

of NWELL)

                                    Oven bake (30 min., 120 C)

    ________________________________________________________________________

10.0 Nitride Etch:

Plasma etch nitride in lam4.    Recipe: 200

Power: 125 W         Time:~85 sec.        Overetch: no

Selectivity: Si3N4:PR=1:1

Measure Tox on each work wafer. (2 pnts measurement).

Do not remove PR. Inspect.

Measure PR thickness covering active area.tpr >= 700nm

Hard bake again ( 2 hours, 120 C)

    ________________________________________________________________________

11.0 P-Well implant:

Boron, 5E12, 60KeV

                                    Include NCH.

    ________________________________________________________________________

12.0 Nitride removal:

    _______________________________________________________________________

                        12.1. Remove PR in Matrix. Clean wafers in sink9 MEMS piranha

    _______________________________________________________________________

12.2. Etch nitride in fresh 160 C phosphoric acid in sink7 (~4 hours)

    ________________________________________________________________________

                        12.3. Etch pad oxide in 5:1 BHF at sink7 until dewet. Include NCH, PCH.

    ________________________________________________________________________

13.0 Well Drive-In:

    ________________________________________________________________________

13.1 TLC clean furnace tube (tystar2).

    _______________________________________________________________________

13.2 Standard clean wafers in sink9 (MEMS and MOS).

                                    Include NCH, PCH control wafers.

   ________________________________________________________________________

13.3 Well drive in at 1100 C (2WELLDR):

                        60 min. temperature ramp from 750 C to 1100 C

150 min. dry O2

                        15 min. N2

                                    Measure oxide thickness on two wafers.

    ________________________________________________________________________

                        13.4 Strip oxide in 5:1 BHF until dewet.

                                    Measure Rs on PCH, NCH

    ________________________________________________________________________

            14.0 Pad Oxidation/Nitride Deposition:

Target = 25 nm SiO2 + 180 nm Si3N4

    ________________________________________________________________________

14.1 TLC clean furnace tube (tystar2). Reserve tystar9.

    _______________________________________________________________________

14.2 Standard clean wafers in sink9 (MEMS, MOS, 25:1 dip

until dewet.) Include NCH, PCH + 2 dummies.

    ________________________________________________________________________

14.3 Dry oxidation at 1000 C (2DRYOXA):

21 min. dry O2

15 minutes dry N2 anneal.

Measure the oxide thickness on NCH.

    ________________________________________________________________________

14.4 Deposit 180 nm of Si3N4 immediately (9SNITA):

Approx. time = 55 min., temp = 800 C.

Only include PCH.

Measure nitride thickness on PCH.

    ________________________________________________________________________

15.0 Active Area Photo: 

Std. DUV litho process. Mask ACTV,

Oven bake 120C, 2 hrs.

    ________________________________________________________________________

16.0 Nitride Etch:

Plasma etch nitride in lam4.    Recipe: 200

Power: 125 W         Time:~90 sec.        Overetch: no

Measure Tox on each work wafer (2 points measurement).

    ________________________________________________________________________

            17.0 P-Well Field Implant Photo

                                    Std. DUV process. Mask PFIELD (inverse of NWELL+ACT)

Oven bake 120 C, 2hrs.

    ________________________________________________________________________

            18.0 P-Well Field Ion Implant

                                    Boron, 2E13, 80KeV

    ________________________________________________________________________

            19.0 Locos Oxidation:  target = 550 nm

    ________________________________________________________________________

19.1 TLC clean furnace tube (tystar2).

    ________________________________________________________________________

                        19.2 Remove PR in O2 plasma (matrix).

Standard clean wafers in sink8 MEMS & sink6 MOS piranha,

25:1 HF dip for 5-10 sec.)

Include NCH, PCH.

    ________________________________________________________________________

19.3 Wet oxidation at 1000 C (2WETOXA):

                        2 hrs. wet O2

                        20 min. N2 anneal

Measure Tox on 3 work wafers and NCH, PCH.

    _______________________________________________________________________

20.0 Nitride Removal, Pad Oxide Removal.

Include PCH (NCH: no nitride, but LOCOS).

                                    Dip in 10:1 HF for 60 sec to remove thin oxide on top of Si3N4.

                                    Etch nitride off in phosphoric acid at 160 C. (sink7) ~3-4 hrs.

                                    Measure pad oxide thickness to verify successful nitride etch.

                                    Etch pad oxide in 5:1 BHF until PCH control wafer dewet.

                                    Etch LOCOS from NCH in 5:1 BHF until dewet.

    ________________________________________________________________________

            21.0 Sacrificial oxidation. (Target = 250A)

    ________________________________________________________________________

21.1 TLC clean furnace tube (tystar2).

    _______________________________________________________________________

21.2 Standard clean wafers in sink8 MEMS & sink6 MOS piranha,

            25:1 HF dip for 5-10 sec)

            Include NCH, PCH.

    ________________________________________________________________________

                        21.3 Dry oxidation at 900 C (2DRYOXA):

40 min. dry O2

no N2 anneal (set to 1 sec)

Measure the oxide thickness on NCH.

 

    ________________________________________________________________________

            22.0 Screen oxidation. Include NCH, PCH

    ________________________________________________________________________

22.1 TLC clean furnace tube (tystar2).

    ________________________________________________________________________

22.2 Standard clean wafers sink6 MOS piranha, dip in 25:1 HF until

NCH, PCH dewet to remove sacr. oxide on active area

(Keep in mind you have LOCOS !)

    ________________________________________________________________________

22.3 Sacrificial Oxide: target = 25 (+/- 2) nm

Dry oxidation at 900 C (2DRYOXA):

                        40 minutes dry O2

                        15 minutes N2 anneal

                        Measure Tox on PCH. 

    ________________________________________________________________________

            23.0 NMOS Vt implant photo

                                    Std. DUV litho. Mask PWELL. UVBAKE (pr. J)

    ________________________________________________________________________

            24.0 NMOS Vt implant

                                    Split: BF2, 4E12, 50KeV, w# 1, 2, 3, 9, 10, NCH.

                                             BF2, 6E12, 50KeV, W# 4, 5, 6, 7, 8

    ________________________________________________________________________

            25.0 PMOS Vt implant photo

                                    Remove PR in matrix, sink8 MEMS piranha clean

                                    Std. DUV litho. Mask NWELL. UVBAKE (pr. J)

    ________________________________________________________________________

            26.0 PMOS Vt implant: split: phosphorus, 30 KeV, 2E12/cm2, w#1-5, PCH

        phosphorus, 30KeV, 1E12/cm2, w#6-10.

    ________________________________________________________________________

27.0 Gate Oxidation/Poly-Si Deposition:

Target = 8 nm SiO2 + 250 nm undoped poly-Si

    ________________________________________________________________________

27.1 TLC clean furnace tube (tystar1).

                        Reserve poly-Si deposition tube (tystar10).

    ________________________________________________________________________

 

27.2 Remove PR in Matrix.

Standard clean wafers sink8 MEMS, sink6 MOS piranha,

25:1 HF dip until dewet on PCH, NCH approx. 2-3 min.

Include Tox (prime P<100>), Tpoly1, Tpoly2 monitoring wafers.

    ________________________________________________________________________

27.3 Dry oxidation in Tystar1 recipe 1THIN-OX

30 min. dry O2 @ 850C

30 min. N2 anneal @ 900 C

Include PCH, NCH, Tox, Tpoly1, Tpoly2 and 3 test dummies.

Note: ALMACK step 25 in furnace process unless the

pre-oxidation furnace temp. is 450C

    ________________________________________________________________________

27.4 Immediately after oxidation deposit 250 nm of undoped

                        poly-Si (10suplya).

approx. dep. rate= 85 A/min.,  temp.= 610 C

(Check previous run result)

Include Tpoly1, Tpoly2 and the 3 test dummies.

    ________________________________________________________________________

27.5 Measurements

a) Measure oxide thickness on Tox. (Rudolph and Sopra ell.)

b) Measure Dit and Qox on Tox. (SCA)

c) Measure poly thickness on Tpoly1. (Nanoduv)

d) Stip oxide from NCH, PCH, measure the sheet resisitance.

    ________________________________________________________________________

28.0 Gate Definition:

                        Standard DUV lithography process.

Mask POLY, Use ARC-600, UVBAKE (U

    ________________________________________________________________________

29.0 Plasma etch poly-Si

    ________________________________________________________________________

29.1 Etch poly in Lam5. Recipe: 5003 with modified over etch step:

Pwr:250 W top, 125W bottom; 200sccm HBr, 5sccm O2,

0sccm He. Selectivity ~60:1 poly to oxide.

Apply ~50% over etch after endpoint in main etch.

    ________________________________________________________________________

29.2 Remove PR (matrix), clean wafers in MEMS piranha.

                        Measure channel length with CDSEM.

    ________________________________________________________________________

            30.0 P-type LDD implant photo

                                    Std. DUV lithography. Mask modified P+S/D. UVBAKE pr. J

    ________________________________________________________________________

31.0 P-type LDD implant. Include PCH, Tpoly1.

BF2, 5e13, 10KeV +7 deg. tilt @ 0 orientation

BF2, 5e13, 10KeV -7 deg. tilt @ 180 orientation

    ________________________________________________________________________

32.0 N-type LDD implant photo

                        Remove PR in Matrix. Clean wafers in sink8 MEMS piranha.

                        Std. DUV litho. Mask modified N+S/D. UVBAKE pr. J

    ________________________________________________________________________

33.0 N-type LDD implant. Include NCH, Tpoly2.

As, 5e13, 30KeV +7 deg. tilt @ 0 orientation

As, 5e13, 30KeV -7 deg. tilt @ 180 orientation

    ________________________________________________________________________

34.0 LDD Spacer deposition (spacer width target= 3000 A)

    ________________________________________________________________________

34.1 Remove PR in matrix.

Standard clean wafers (sink8 MEMS, sink6 MOS)

Include 3 dummies.

Reserve and TLC clean tystar2.

    ________________________________________________________________________

34.2 TEOS deposition in P-5000 target=4000-4500 A

Check dep. rate (~ 80 A/min.)

    ________________________________________________________________________

34.3 TEOS annealing 900 C, 30 min. (2HIN2ANA)

    ________________________________________________________________________ 

34.4 Measure TEOS thickness on active area.

    ________________________________________________________________________

35.0 LDD Spacer Formation

    ________________________________________________________________________

35.1 Plasma etch TEOS in Applied-Centura

Verify actual etch rate (~3000 A/min)

Recipe MXP_OXSP_ETCH_EP

Manual endpoint when signal drops

    ________________________________________________________________________

35.2 Measure spacer with CDSEM.

    ________________________________________________________________________

 

36.0 P+ Gate & S/D Photo:

Standard DUV Lithography process.

Mask 2nd modified P+ S/D, UVBAKE (“J”)

    ________________________________________________________________________

37.0 P+ Gate & S/D Implant. Include PCH, Tpoly1.

B11, 20 keV, 3E15/cm2

    ________________________________________________________________________

38.0 N+ Gate & S/D Photo:

    _______________________________________________________________________

            38.1 Remove PR in Matrix. Std. Clean wafers in sink8 MEMS piranha.

    _______________________________________________________________________

38.2 Standard DUV Lithography process.

            Mask 2nd modified N+ S/D, UVBAKE (“J”)

    ________________________________________________________________________

39.0 N+ Gate & S/D Implant. Include NCH and Tpoly2.

Phosphorus, 40 KeV, 3E15/cm2

    ________________________________________________________________________

40.0 Back Side Etch:

    _______________________________________________________________________

40.1 Remove PR in O2 plasma (matrix), piranha clean wafers in

sink8 MEMS side (no dip).

Dehydrate wafers in oven at 120 C for >30 min.

    _______________________________________________________________________

 

40.2      a) Coat wafers front side, UVBAKE

b) Dip off native oxide in 5:1 BHF in sink8

c) Etch poly-Si in lam5, recipe 5003, no over etch

            Etch to endpoint plus 10 sec.

d) Final dip in 5:1 BHF until dewet (~1min)

            Incl. NCH, PCH, TPoly1, Tpoly2 to remove

            native oxide (~20 sec)

    _______________________________________________________________________

41.0 Gate & S/D annealing. Include all test wafers.

    ________________________________________________________________________

41.1 Remove PR in matrix.

    ________________________________________________________________________

41.2 Standard clean wafers in sink8 MEMS and sink6 MOS, no dip

    ________________________________________________________________________

41.3 RTA in Heatpulse3, recipe 1050RTA.RCP

900 C, 10 sec., 1050 C, 5 sec in N2

    ________________________________________________________________________

                        41.4 Check Rs on test wafers: for gate < 250 ohm/sq, for S/D <100.

    ________________________________________________________________________

            42.0 Silicide

42.1 Sputter etch in Novellus (ETCHSTD 1 min) or 25:1 HF dip 30 sec

42.2 Sputter 300 Ti in Novellus (Ti300STD). Measure Rs.

42.3 RTA 650 C, 15 sec in N2. Recipe 650RTA6.RCP

42.4 Etch excess Ti/TiN in piranha (120 C, 45 min.) in Sink7.

            Measure contact resistance.

    ________________________________________________________________________

43.0 PSG deposition and densification: target 700 nm

    ________________________________________________________________________

43.1 Clean wafers in sink6 MEMS & sink8 MOS side, NO HF dip!

Include PCH and PSG control wafers.

    ________________________________________________________________________

43.2 Deposit 700 nm PSG in tystar11 (11SDLTOA)

Deposition time is approx.: 53 min., 450 C

    ________________________________________________________________________

43.3 Backside etch PSG.

              - Coat wafers and UVBAKE pr. J

              - Dip into 5:1 BHF until backside dewet

              - Matrix PR removal

- Sink8 MEMS & Sink6 MOS piranha clean

    ________________________________________________________________________

43.4 Densify PSG in RTA (heatpulse3). Recipe 900RTA.RCP

900 C, 10 sec, (450 C, 30 sec pre-heat step), silicide chamber.

    ________________________________________________________________________

43.4 Measure PSG thickness on PSG control wafer. Etch (wet) oxide on

PCH and measure RS.

    ________________________________________________________________________

 

            44.0 Contact Photo:

                                    Standard DUV lithography process. Use ARC-600.

2nd modified CONT mask. Over-expose contact (30-40 mJ/cm2)

                                    Second PM mark should be exposed, before developing

Oven bake (60 min., 120 C).

    ________________________________________________________________________

 

45.0 Contact plasma etch in Applied Centura.

Recipe: MXP_OXSP_ETCH_EP

overetch: 15 sec after endpoint signal drops

Measure R with manual probe on Poly and S/D area on each wafer.

R~10-100Ohm Check contact holes structure.

    ________________________________________________________________________

            46.0 Metallization: target= 600 nm Al

    ________________________________________________________________________

46.1 Remove PR in O2 plasma (Matrix).

    ________________________________________________________________________

46.2 Standard clean wafers in sink8 MEMS no dip, sink6 MOS piranha

Either 25:1/100:1 HF dip 60 sec or Novellus sputter etch to remove native oxide

    ________________________________________________________________________

46.3 Sputter Al/2%Si in Novellus:

                                    AL7STD, Measure Rs

    ________________________________________________________________________

47.0 Metal1 Photo:

Standard DUV litho. process, ARC-600.

Mask METAL1. UVBAKE pr. U

    ________________________________________________________________________

48.0 Plasma etch metal1 in lam3.

                                    Standard recipe: approx. time: 1min 25 sec, overetch= 50 %

                                    Check R on Fieldox.

    ________________________________________________________________________

49.0 Sintering

49.1 Remove PR in matrix. Rinse & spin dry at sink8.

49.2 Sinter in Tystar18 H2SINT4A.018 recipe 20 min @ 400 C

    ________________________________________________________________________

50.0 TESTING