INTRODUCTION
 
The Microfabrication Laboratory at the University of California, Berkeley
has been supporting silicon MOS technology from the time the present VLSI
facility was opened in 1983 [1,2]. 
 
The BASELINE has always specified standard process modules for VLSI
operations, provided test circuits, and a starting point for development
by various research groups such as Berkeley Sensor and Actuator Center (BSAC), 
Berkeley Computer Aided Manufacturing group, and Berkeley Microfabrication 
Laboratory affiliates [3, 4, 5]. 
 
Baseline runs, in conjunction with in-line equipment monitoring,
have provided an excellent means for staff to quickly discover/address 
possible equipment/process problems in the Microlab. Baseline runs have 
also played an important role in releasing new and upgraded tools, 
as well as pushing out the performance of high-end equipment.
 
The first CMOS baseline report [6] described a 2.5um, n-well, double poly-Si, 
and double metal CMOS process. This process was subsequently developed into 
a twin-well, 1.3um, double poly-Si, double metal process.[7] 
 
The same process was also used for the fabrication of our first six-inch run 
(CMOS150), which played an important role in releasing six-inch equipment/
processes in the Microlab. Electrical (parametric) test results, comparable 
to the previous four-inch runs were realized, which confirmed that the 
six-inch conversion project was a success, report [8].
 
CMOS baseline runs had been processed regularly on 4 inch wafers up until
2001; after the first six-inch run (CMOS 150), which successfully transferred 
the baseline process onto six-inch wafers, a new and more advanced, 0.35 um 
process was developed (CMOS161). 
 
Complete reports can be accessed through the Baseline Reports panel
of this web portal.
 
A. Horvath
S. Parsa
K. Voros
2005
 
REFERENCES
 
[1] Katalin Voros and Ping K. Ko, MOS Processes in the Microfabrication
Laboratory, Memorandum No. UCB/ERL M87/12, Electronics Research Laboratory,
University of California, Berkeley (10 March 1987)
 
[2] Katalin Voros and Ping K.Ko, Evolution of the Microfabrication Facility
at Berkeley, Memorandum No. UCB/ERL M89/109, Electronics Research
Laboratory, University of California, Berkeley (22 September 1989)
 
[3] Andrea E. Franke, Polycrystalline Silicon-Germanium Films for Integrated
Microsystems, PhD dissertation, Department of Electrical Engineering and
Computer Sciences, University of California, Berkeley, (December 2000)
 
[4] Paul M. Krueger, Tuning a Statistical Process Simulator to a Berkeley
CMOS Process, Memorandum No. UCB/ERL M88/82, Electronics Research
Laboratory, University of California (15 December 1988)
 
[5] David Rodriguez, Electrical Testing of a CMOS Baseline Process,
Memorandum No. UCB/ERL M94/63, Electronics Research Laboratory, University
of California, Berkeley (30 August 1994)
 
[6] Shenqing Fang, CMOS Baseline process in the UC Berkeley Microfabrication
Laboratory, Memorandum No. UCB/ERL M95/98, Electronics Research Laboratory,
University of California, Berkeley (20 December 1995)
 
[6] Laszlo Voros, CMOS Baseline process in the UC Berkeley Microfabrication
Laboratory, Memorandum No. UCB/ERL M00/61, Electronics Research Laboratory,
University of California, Berkeley (7 December 2000)
 
[7] Laszlo Voros and Sia Parsa, Six-inch CMOS Baseline process in the UC
Berkeley Microfabrication Laboratory, Memorandum No. UCB/ERL M02/39,
Electronics Research Laboratory, University of California, Berkeley 
(1 December 2002)